@@ -1033,7 +1033,9 @@ static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev,
10331033 /* Until a uniform way is figured, get mask based on hwid */
10341034 switch (hw_id ) {
10351035 case VCN_HWID :
1036- harvest = ((1 << inst ) & adev -> vcn .inst_mask ) == 0 ;
1036+ /* VCN vs UVD+VCE */
1037+ if (!amdgpu_ip_version (adev , VCE_HWIP , 0 ))
1038+ harvest = ((1 << inst ) & adev -> vcn .inst_mask ) == 0 ;
10371039 break ;
10381040 case DMU_HWID :
10391041 if (adev -> harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK )
@@ -2565,7 +2567,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
25652567 amdgpu_discovery_init (adev );
25662568 vega10_reg_base_init (adev );
25672569 adev -> sdma .num_instances = 2 ;
2570+ adev -> sdma .sdma_mask = 3 ;
25682571 adev -> gmc .num_umc = 4 ;
2572+ adev -> gfx .xcc_mask = 1 ;
25692573 adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (9 , 0 , 0 );
25702574 adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (9 , 0 , 0 );
25712575 adev -> ip_versions [OSSSYS_HWIP ][0 ] = IP_VERSION (4 , 0 , 0 );
@@ -2592,7 +2596,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
25922596 amdgpu_discovery_init (adev );
25932597 vega10_reg_base_init (adev );
25942598 adev -> sdma .num_instances = 2 ;
2599+ adev -> sdma .sdma_mask = 3 ;
25952600 adev -> gmc .num_umc = 4 ;
2601+ adev -> gfx .xcc_mask = 1 ;
25962602 adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (9 , 3 , 0 );
25972603 adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (9 , 3 , 0 );
25982604 adev -> ip_versions [OSSSYS_HWIP ][0 ] = IP_VERSION (4 , 0 , 1 );
@@ -2619,8 +2625,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
26192625 amdgpu_discovery_init (adev );
26202626 vega10_reg_base_init (adev );
26212627 adev -> sdma .num_instances = 1 ;
2628+ adev -> sdma .sdma_mask = 1 ;
26222629 adev -> vcn .num_vcn_inst = 1 ;
26232630 adev -> gmc .num_umc = 2 ;
2631+ adev -> gfx .xcc_mask = 1 ;
26242632 if (adev -> apu_flags & AMD_APU_IS_RAVEN2 ) {
26252633 adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (9 , 2 , 0 );
26262634 adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (9 , 2 , 0 );
@@ -2665,7 +2673,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
26652673 amdgpu_discovery_init (adev );
26662674 vega20_reg_base_init (adev );
26672675 adev -> sdma .num_instances = 2 ;
2676+ adev -> sdma .sdma_mask = 3 ;
26682677 adev -> gmc .num_umc = 8 ;
2678+ adev -> gfx .xcc_mask = 1 ;
26692679 adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (9 , 4 , 0 );
26702680 adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (9 , 4 , 0 );
26712681 adev -> ip_versions [OSSSYS_HWIP ][0 ] = IP_VERSION (4 , 2 , 0 );
@@ -2693,8 +2703,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
26932703 amdgpu_discovery_init (adev );
26942704 arct_reg_base_init (adev );
26952705 adev -> sdma .num_instances = 8 ;
2706+ adev -> sdma .sdma_mask = 0xff ;
26962707 adev -> vcn .num_vcn_inst = 2 ;
26972708 adev -> gmc .num_umc = 8 ;
2709+ adev -> gfx .xcc_mask = 1 ;
26982710 adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (9 , 4 , 1 );
26992711 adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (9 , 4 , 1 );
27002712 adev -> ip_versions [OSSSYS_HWIP ][0 ] = IP_VERSION (4 , 2 , 1 );
@@ -2726,8 +2738,10 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
27262738 amdgpu_discovery_init (adev );
27272739 aldebaran_reg_base_init (adev );
27282740 adev -> sdma .num_instances = 5 ;
2741+ adev -> sdma .sdma_mask = 0x1f ;
27292742 adev -> vcn .num_vcn_inst = 2 ;
27302743 adev -> gmc .num_umc = 4 ;
2744+ adev -> gfx .xcc_mask = 1 ;
27312745 adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (9 , 4 , 2 );
27322746 adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (9 , 4 , 2 );
27332747 adev -> ip_versions [OSSSYS_HWIP ][0 ] = IP_VERSION (4 , 4 , 0 );
@@ -2762,6 +2776,8 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
27622776 } else {
27632777 cyan_skillfish_reg_base_init (adev );
27642778 adev -> sdma .num_instances = 2 ;
2779+ adev -> sdma .sdma_mask = 3 ;
2780+ adev -> gfx .xcc_mask = 1 ;
27652781 adev -> ip_versions [MMHUB_HWIP ][0 ] = IP_VERSION (2 , 0 , 3 );
27662782 adev -> ip_versions [ATHUB_HWIP ][0 ] = IP_VERSION (2 , 0 , 3 );
27672783 adev -> ip_versions [OSSSYS_HWIP ][0 ] = IP_VERSION (5 , 0 , 1 );
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