Overhaul "Pixel FIFO" article into "Rendering Internals"

Also avoid describing SameBoy internals, instead relying on it when
otherwise corroborated, or on schematics and/or test ROMs when possible.

Restructure the article to describe behavior more than components, especially
in a way that is more friendly to someone not knowing what all the components
are about.

Add a diagram, too, and move the mode timing diagram to the STAT article, where
it belongs just as well, but where it will be more visible and thus more useful.

Author: ISSOtm

custom/style.css

@@ -100,6 +100,13 @@ code {
 }
 
 
+/* Classes for custom table styling */
+
+table.compact th {
+    padding: 3px 5px;
+}
+
+
 /* Global CSS variables */
 
 :root {

src/Rendering_Internals.md

@@ -2,7 +2,7 @@
 
 ::: tip TERMINOLOGY
 
-A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-state on DMG or on CGB single-speed mode or 2 T-states on CGB double-speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Pixel FIFO>).
+A *dot* is the shortest period over which the PPU can output one pixel: is it equivalent to 1 T-state on DMG or on CGB single-speed mode or 2 T-states on CGB double-speed mode. On each dot during mode 3, either the PPU outputs a pixel or the fetcher is stalling the [FIFOs](<#Rendering Internals>).
 
 :::
 
@@ -56,11 +56,13 @@ Mode | Action                                                      | Duration
   0  | Nothing (HBlank)                               | 85 to 208 dots (20 to 49 µs) depending on previous mode 3 duration | VRAM, OAM, CGB palettes
   1  | Nothing (VBlank)                                 | 4560 dots (1087 µs, 10 scanlines)                                  | VRAM, OAM, CGB palettes
 
-## Properties of STAT modes
+## STAT modes
+
+{{#include imgs/ppu_modes_timing.svg:2:}}
 
 Unlike most game consoles, the Game Boy can pause the dot clock briefly,
 making Mode 3 longer and Mode 0 shorter. It routinely takes a 6 to 11 dot
-break to fetch an OBJ's tile between background tile pattern fetches.
+break to fetch an OBJ's tile between background tile fetches.
 On DMG and GBC in DMG mode, mid-scanline writes to [`BGP`](<#FF47 - BGP (BG Palette Data) (R/W) - Non CGB Mode Only>)
 allow observing this behavior, as the delay from drawing an OBJ shifts the
 write's effect to the left by that many dots.

src/STAT.md

@@ -23,7 +23,7 @@
   - [LCD Status](./STAT.md)
   - [Scrolling](./Scrolling.md)
   - [Palettes](./Palettes.md)
-  - [Pixel FIFO](./pixel_fifo.md)
+  - [Rendering internals](./Rendering_Internals.md)
 - [Sound Controller](./Sound_Controller.md)
 - [Joypad Input](./Joypad_Input.md)
 - [Serial Data Transfer](./Serial_Data_Transfer_(Link_Cable).md)

src/SUMMARY.md

@@ -48,7 +48,7 @@ scanline.
 
 ### Scrolling
 
-The scroll registers are re-read on each [tile fetch](<#Get Tile>), except for the low 3 bits of SCX, which are only read at the beginning of the scanline (for the initial shifting of pixels).
+The scroll registers are re-read on each [tile fetch](<#Get tile ID>), except for the low 3 bits of SCX, which are only read at the beginning of the scanline (for the initial shifting of pixels).
 
 All models before the CGB-D read the Y coordinate once for each bitplane (so a very precisely timed SCY write allows "desyncing" them), but CGB-D and later use the same Y coordinate for both no matter what.