Add better optimization flags for Intel compilers on AMD systems

Intel will use SSE2 when passed -xHost on AMD systems
Be more specific here by passing e.g. AVX2 when that is available.

Author: Flamefire

easybuild/toolchains/compiler/inteliccifort.py

@@ -72,13 +72,15 @@ class IntelIccIfort(Compiler):
 
     # used when 'optarch' toolchain option is enabled (and --optarch is not specified)
     COMPILER_OPTIMAL_ARCHITECTURE_OPTION = {
-        (systemtools.X86_64, systemtools.AMD): 'xHost',
-        (systemtools.X86_64, systemtools.INTEL): 'xHost',
+        systemtools.X86_64: 'xHost',
+        # Intel compilers don't auto-detect AMD features and default to SSE2
+        (systemtools.X86_64, systemtools.AMD, systemtools.SSSE3): 'mssse3',
+        (systemtools.X86_64, systemtools.AMD, systemtools.SSE4_2): 'msse4.2',
+        (systemtools.X86_64, systemtools.AMD, systemtools.AVX2): 'march=core-avx2',
     }
     # used with --optarch=GENERIC
     COMPILER_GENERIC_OPTION = {
-        (systemtools.X86_64, systemtools.AMD): 'xSSE2',
-        (systemtools.X86_64, systemtools.INTEL): 'xSSE2',
+        systemtools.X86_64: 'xSSE2',
     }
 
     COMPILER_CC = 'icc'

easybuild/tools/systemtools.py

@@ -84,6 +84,9 @@
 # Vector extension constants
 SSE = 'sse'
 SSE2 = 'sse2'
+SSSE3 = 'ssse3'
+SSE4_1 = 'sse4_1'
+SSE4_2 = 'sse4_2'
 AVX = 'avx'
 AVX2 = 'avx2'
 AVX512F = 'avx512f'
@@ -120,7 +123,7 @@
 CPU_FAMILIES = [AMD, ARM, INTEL, POWER, POWER_LE]
 CPU_VENDORS = [AMD, APM, ARM, BROADCOM, CAVIUM, DEC, IBM, INTEL, MARVELL, MOTOROLA, NVIDIA, QUALCOMM]
 # Vector extensions of CPUs in ascending order (later => better)
-CPU_VECTOR_EXTS = [SSE, SSE2, AVX, AVX2, AVX512F]
+CPU_VECTOR_EXTS = [SSE, SSE2, SSSE3, SSE4_1, SSE4_2, AVX, AVX2, AVX512F]
 # ARM implementer IDs (i.e., the hexadeximal keys) taken from ARMv8-A Architecture Reference Manual
 # (ARM DDI 0487A.j, Section G6.2.102, Page G6-4493)
 VENDOR_IDS = {