diff --git a/src/coreclr/jit/fgdiagnostic.cpp b/src/coreclr/jit/fgdiagnostic.cpp index f32e14ad4b1e13..889490925adf10 100644 --- a/src/coreclr/jit/fgdiagnostic.cpp +++ b/src/coreclr/jit/fgdiagnostic.cpp @@ -3458,10 +3458,10 @@ void Compiler::fgDebugCheckFlags(GenTree* tree, BasicBlock* block) case NI_Sve_GatherPrefetch32Bit: case NI_Sve_GatherPrefetch64Bit: case NI_Sve_GatherPrefetch8Bit: - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: case NI_Sve_GetFfrByte: case NI_Sve_GetFfrInt16: case NI_Sve_GetFfrInt32: diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp index 0baf062913bdc8..e2b4456425cef5 100644 --- a/src/coreclr/jit/gentree.cpp +++ b/src/coreclr/jit/gentree.cpp @@ -28698,10 +28698,6 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const #if defined(TARGET_ARM64) case NI_ArmBase_Yield: - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: case NI_Sve_GatherPrefetch16Bit: case NI_Sve_GatherPrefetch32Bit: case NI_Sve_GatherPrefetch64Bit: @@ -28714,6 +28710,10 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const case NI_Sve_GetFfrUInt16: case NI_Sve_GetFfrUInt32: case NI_Sve_GetFfrUInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: case NI_Sve_SetFfr: { return true; @@ -28916,10 +28916,10 @@ void GenTreeHWIntrinsic::Initialize(NamedIntrinsic intrinsicId) case NI_Sve_GatherPrefetch32Bit: case NI_Sve_GatherPrefetch64Bit: case NI_Sve_GatherPrefetch8Bit: - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: case NI_Sve_GetFfrByte: case NI_Sve_GetFfrInt16: case NI_Sve_GetFfrInt32: diff --git a/src/coreclr/jit/hwintrinsicarm64.cpp b/src/coreclr/jit/hwintrinsicarm64.cpp index 06b6b1edf77aa6..5a5fd9ba972777 100644 --- a/src/coreclr/jit/hwintrinsicarm64.cpp +++ b/src/coreclr/jit/hwintrinsicarm64.cpp @@ -508,10 +508,10 @@ void HWIntrinsicInfo::lookupImmBounds( case NI_Sve_GatherPrefetch16Bit: case NI_Sve_GatherPrefetch32Bit: case NI_Sve_GatherPrefetch64Bit: - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: immLowerBound = (int)SVE_PRFOP_PLDL1KEEP; immUpperBound = (int)SVE_PRFOP_CONST15; break; @@ -3182,10 +3182,10 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic, case NI_Sve_GatherPrefetch16Bit: case NI_Sve_GatherPrefetch32Bit: case NI_Sve_GatherPrefetch64Bit: - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: { assert((sig->numArgs == 3) || (sig->numArgs == 4)); assert(!isScalar); diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index 1ce3b282f6673a..2120cbc1d04911 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -1786,10 +1786,10 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) break; } - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: { assert(hasImmediateOperand); HWIntrinsicImmOpHelper helper(this, intrin.op3, node); diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h index 639a9056a1b608..1554efbb62f5a3 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64sve.h +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -227,10 +227,10 @@ HARDWARE_INTRINSIC(Sve, Not, HARDWARE_INTRINSIC(Sve, Or, -1, -1, {INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_HasAllMaskVariant) HARDWARE_INTRINSIC(Sve, OrAcross, -1, -1, {INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_ReduceOperation) HARDWARE_INTRINSIC(Sve, PopCount, -1, -1, {INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) -HARDWARE_INTRINSIC(Sve, PrefetchBytes, -1, 3, {INS_invalid, INS_sve_prfb, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) -HARDWARE_INTRINSIC(Sve, PrefetchInt16, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_sve_prfh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) -HARDWARE_INTRINSIC(Sve, PrefetchInt32, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) -HARDWARE_INTRINSIC(Sve, PrefetchInt64, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfd, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) +HARDWARE_INTRINSIC(Sve, Prefetch16Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_sve_prfh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) +HARDWARE_INTRINSIC(Sve, Prefetch32Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) +HARDWARE_INTRINSIC(Sve, Prefetch64Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfd, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) +HARDWARE_INTRINSIC(Sve, Prefetch8Bit, -1, 3, {INS_invalid, INS_sve_prfb, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) HARDWARE_INTRINSIC(Sve, ReciprocalEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frecpe, INS_sve_frecpe}, HW_Category_SIMD, HW_Flag_Scalable) HARDWARE_INTRINSIC(Sve, ReciprocalExponent, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frecpx, INS_sve_frecpx}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, ReciprocalSqrtEstimate, -1, 1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_frsqrte, INS_sve_frsqrte}, HW_Category_SIMD, HW_Flag_Scalable) diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index 38d6cb6cf6ba41..a1fe92920ae2cc 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -3820,10 +3820,10 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node) case NI_AdvSimd_ExtractVector128: case NI_AdvSimd_StoreSelectedScalar: case NI_AdvSimd_Arm64_StoreSelectedScalar: - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: case NI_Sve_ExtractVector: case NI_Sve_AddRotateComplex: case NI_Sve_TrigonometricMultiplyAddCoefficient: diff --git a/src/coreclr/jit/lsraarm64.cpp b/src/coreclr/jit/lsraarm64.cpp index 24cd1bd4a818aa..c0a25631715890 100644 --- a/src/coreclr/jit/lsraarm64.cpp +++ b/src/coreclr/jit/lsraarm64.cpp @@ -1655,10 +1655,10 @@ void LinearScan::BuildHWIntrinsicImmediate(GenTreeHWIntrinsic* intrinsicTree, co case NI_AdvSimd_ExtractVector128: case NI_AdvSimd_StoreSelectedScalar: case NI_AdvSimd_Arm64_StoreSelectedScalar: - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: case NI_Sve_ExtractVector: case NI_Sve_TrigonometricMultiplyAddCoefficient: needBranchTargetReg = !intrin.op3->isContainedIntOrIImmed(); @@ -2356,14 +2356,14 @@ GenTree* LinearScan::getVectorAddrOperand(GenTreeHWIntrinsic* intrinsicTree) // Operands that are not loads or stores but do require an address switch (intrinsicTree->GetHWIntrinsicId()) { - case NI_Sve_PrefetchBytes: - case NI_Sve_PrefetchInt16: - case NI_Sve_PrefetchInt32: - case NI_Sve_PrefetchInt64: case NI_Sve_GatherPrefetch8Bit: case NI_Sve_GatherPrefetch16Bit: case NI_Sve_GatherPrefetch32Bit: case NI_Sve_GatherPrefetch64Bit: + case NI_Sve_Prefetch16Bit: + case NI_Sve_Prefetch32Bit: + case NI_Sve_Prefetch64Bit: + case NI_Sve_Prefetch8Bit: if (!varTypeIsSIMD(intrinsicTree->Op(2)->gtType)) { return intrinsicTree->Op(2); diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs index ae59a6fb4f8ed7..edd5835b8b37ca 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs @@ -7422,22 +7422,13 @@ internal Arm64() { } public static Vector PopCount(Vector value) { throw new PlatformNotSupportedException(); } - // Prefetch bytes - - /// - /// void svprfb(svbool_t pg, const void *base, enum svprfop op) - /// PRFB op, Pg, [Xbase, #0, MUL VL] - /// - public static unsafe void PrefetchBytes(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } - - // Prefetch halfwords /// /// void svprfh(svbool_t pg, const void *base, enum svprfop op) /// PRFH op, Pg, [Xbase, #0, MUL VL] /// - public static unsafe void PrefetchInt16(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } + public static unsafe void Prefetch16Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } // Prefetch words @@ -7446,7 +7437,7 @@ internal Arm64() { } /// void svprfw(svbool_t pg, const void *base, enum svprfop op) /// PRFW op, Pg, [Xbase, #0, MUL VL] /// - public static unsafe void PrefetchInt32(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } + public static unsafe void Prefetch32Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } // Prefetch doublewords @@ -7455,7 +7446,16 @@ internal Arm64() { } /// void svprfd(svbool_t pg, const void *base, enum svprfop op) /// PRFD op, Pg, [Xbase, #0, MUL VL] /// - public static unsafe void PrefetchInt64(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } + public static unsafe void Prefetch64Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } + + + // Prefetch bytes + + /// + /// void svprfb(svbool_t pg, const void *base, enum svprfop op) + /// PRFB op, Pg, [Xbase, #0, MUL VL] + /// + public static unsafe void Prefetch8Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw new PlatformNotSupportedException(); } // Reciprocal estimate diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs index 4664271d600658..9cf0c73acf49b2 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs @@ -7413,22 +7413,13 @@ internal Arm64() { } public static Vector PopCount(Vector value) => PopCount(value); - // Prefetch bytes - - /// - /// void svprfb(svbool_t pg, const void *base, enum svprfop op) - /// PRFB op, Pg, [Xbase, #0, MUL VL] - /// - public static unsafe void PrefetchBytes(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchBytes(mask, address, prefetchType); - - // Prefetch halfwords /// /// void svprfh(svbool_t pg, const void *base, enum svprfop op) /// PRFH op, Pg, [Xbase, #0, MUL VL] /// - public static unsafe void PrefetchInt16(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt16(mask, address, prefetchType); + public static unsafe void Prefetch16Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch16Bit(mask, address, prefetchType); // Prefetch words @@ -7437,7 +7428,7 @@ internal Arm64() { } /// void svprfw(svbool_t pg, const void *base, enum svprfop op) /// PRFW op, Pg, [Xbase, #0, MUL VL] /// - public static unsafe void PrefetchInt32(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt32(mask, address, prefetchType); + public static unsafe void Prefetch32Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch32Bit(mask, address, prefetchType); // Prefetch doublewords @@ -7446,7 +7437,16 @@ internal Arm64() { } /// void svprfd(svbool_t pg, const void *base, enum svprfop op) /// PRFD op, Pg, [Xbase, #0, MUL VL] /// - public static unsafe void PrefetchInt64(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => PrefetchInt64(mask, address, prefetchType); + public static unsafe void Prefetch64Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch64Bit(mask, address, prefetchType); + + + // Prefetch bytes + + /// + /// void svprfb(svbool_t pg, const void *base, enum svprfop op) + /// PRFB op, Pg, [Xbase, #0, MUL VL] + /// + public static unsafe void Prefetch8Bit(Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) => Prefetch8Bit(mask, address, prefetchType); // Reciprocal estimate diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index b27ff60f800823..e6e4d648603ee2 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -5561,10 +5561,10 @@ internal Arm64() { } public static System.Numerics.Vector PopCount(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector PopCount(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector PopCount(System.Numerics.Vector value) { throw null; } - public static unsafe void PrefetchBytes(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } - public static unsafe void PrefetchInt16(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } - public static unsafe void PrefetchInt32(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } - public static unsafe void PrefetchInt64(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } + public static unsafe void Prefetch16Bit(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } + public static unsafe void Prefetch32Bit(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } + public static unsafe void Prefetch64Bit(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } + public static unsafe void Prefetch8Bit(System.Numerics.Vector mask, void* address, [ConstantExpected] SvePrefetchType prefetchType) { throw null; } public static System.Numerics.Vector ReciprocalEstimate(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector ReciprocalEstimate(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector ReciprocalExponent(System.Numerics.Vector value) { throw null; } diff --git a/src/libraries/apicompat/ApiCompatBaseline.NetCoreAppLatestStable.xml b/src/libraries/apicompat/ApiCompatBaseline.NetCoreAppLatestStable.xml index 811dd618a5fa24..4317f49799c665 100644 --- a/src/libraries/apicompat/ApiCompatBaseline.NetCoreAppLatestStable.xml +++ b/src/libraries/apicompat/ApiCompatBaseline.NetCoreAppLatestStable.xml @@ -1,6 +1,30 @@  + + CP0002 + M:System.Runtime.Intrinsics.Arm.Sve.PrefetchBytes(System.Numerics.Vector{System.Byte},System.Void*,System.Runtime.Intrinsics.Arm.SvePrefetchType) + net9.0/System.Runtime.Intrinsics.dll + net10.0/System.Runtime.Intrinsics.dll + + + CP0002 + M:System.Runtime.Intrinsics.Arm.Sve.PrefetchInt16(System.Numerics.Vector{System.UInt16},System.Void*,System.Runtime.Intrinsics.Arm.SvePrefetchType) + net9.0/System.Runtime.Intrinsics.dll + net10.0/System.Runtime.Intrinsics.dll + + + CP0002 + M:System.Runtime.Intrinsics.Arm.Sve.PrefetchInt32(System.Numerics.Vector{System.UInt32},System.Void*,System.Runtime.Intrinsics.Arm.SvePrefetchType) + net9.0/System.Runtime.Intrinsics.dll + net10.0/System.Runtime.Intrinsics.dll + + + CP0002 + M:System.Runtime.Intrinsics.Arm.Sve.PrefetchInt64(System.Numerics.Vector{System.UInt64},System.Void*,System.Runtime.Intrinsics.Arm.SvePrefetchType) + net9.0/System.Runtime.Intrinsics.dll + net10.0/System.Runtime.Intrinsics.dll + CP0015 M:System.Delegate.#ctor(System.Type,System.String)$0:[T:System.Diagnostics.CodeAnalysis.DynamicallyAccessedMembersAttribute] diff --git a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs index e7a5153a0c6da8..b02de9ca09df58 100644 --- a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs +++ b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs @@ -4172,12 +4172,10 @@ ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_PopCount_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PopCount", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["ValidateIterResult"] = "Helpers.BitCount(firstOp[i]) != result[i]", ["GetIterResult"] = "Helpers.BitCount(leftOp[i])"}), ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_PopCount_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PopCount", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.BitCount(firstOp[i]) != result[i]", ["GetIterResult"] = "Helpers.BitCount(leftOp[i])"}), ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_PopCount_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PopCount", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.BitCount(firstOp[i]) != result[i]", ["GetIterResult"] = "Helpers.BitCount(leftOp[i])"}), - - ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_PrefetchBytes", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PrefetchBytes", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["ValidPrefetch"] = "SvePrefetchType.LoadL1Temporal", ["InvalidPrefetch"] = "(SvePrefetchType)100"}), - ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_PrefetchInt16", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PrefetchInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["ValidPrefetch"] = "SvePrefetchType.LoadL2NonTemporal", ["InvalidPrefetch"] = "(SvePrefetchType)18"}), - ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_PrefetchInt32", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PrefetchInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidPrefetch"] = "SvePrefetchType.StoreL3Temporal", ["InvalidPrefetch"] = "(SvePrefetchType)20"}), - ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_PrefetchInt64", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PrefetchInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidPrefetch"] = "SvePrefetchType.StoreL1NonTemporal", ["InvalidPrefetch"] = "(SvePrefetchType)87"}), - + ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_Prefetch16Bit", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Prefetch16Bit", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["ValidPrefetch"] = "SvePrefetchType.LoadL2NonTemporal", ["InvalidPrefetch"] = "(SvePrefetchType)18"}), + ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_Prefetch32Bit", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Prefetch32Bit", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidPrefetch"] = "SvePrefetchType.StoreL3Temporal", ["InvalidPrefetch"] = "(SvePrefetchType)20"}), + ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_Prefetch64Bit", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Prefetch64Bit", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidPrefetch"] = "SvePrefetchType.StoreL1NonTemporal", ["InvalidPrefetch"] = "(SvePrefetchType)87"}), + ("SvePrefetchTest.template", new Dictionary { ["TestName"] = "Sve_Prefetch8Bit", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "Prefetch8Bit", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["ValidPrefetch"] = "SvePrefetchType.LoadL1Temporal", ["InvalidPrefetch"] = "(SvePrefetchType)100"}), ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_ReverseBits_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "ReverseBits", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["ValidateIterResult"] = "result[i] != Helpers.ReverseElementBits(firstOp[i])", ["GetIterResult"] = "Helpers.ReverseElementBits(leftOp[i])"}), ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_ReverseBits_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "ReverseBits", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["ValidateIterResult"] = "result[i] != Helpers.ReverseElementBits(firstOp[i])", ["GetIterResult"] = "Helpers.ReverseElementBits(leftOp[i])"}), ("SveSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_ReverseBits_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "ReverseBits", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "result[i] != Helpers.ReverseElementBits(firstOp[i])", ["GetIterResult"] = "Helpers.ReverseElementBits(leftOp[i])"}),