From 08b1569dc34e7bfa43d01621314f06e4cda94fbe Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Sat, 6 Jul 2024 21:17:10 -0700 Subject: [PATCH 01/10] Fix the reloc type typo --- src/coreclr/jit/emitarm64.cpp | 2 +- .../tools/Common/Compiler/DependencyAnalysis/Relocation.cs | 6 +++--- src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs | 6 +++--- .../Compiler/ObjectWriter/CoffObjectWriter.cs | 2 +- .../tools/superpmi/superpmi-shared/compileresult.cpp | 2 ++ 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index f98264590aedaa..dea329b38ab1b2 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -11349,7 +11349,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) else { // This is second "add" of "add/add" pair - emitRecordRelocation(odst, id->idAddr()->iiaAddr, IMAGE_REL_ARM64_SECREL_LOW12L); + emitRecordRelocation(odst, id->idAddr()->iiaAddr, IMAGE_REL_ARM64_SECREL_LOW12A); } } else diff --git a/src/coreclr/tools/Common/Compiler/DependencyAnalysis/Relocation.cs b/src/coreclr/tools/Common/Compiler/DependencyAnalysis/Relocation.cs index cba453eff5489c..07d9d0ccb4a061 100644 --- a/src/coreclr/tools/Common/Compiler/DependencyAnalysis/Relocation.cs +++ b/src/coreclr/tools/Common/Compiler/DependencyAnalysis/Relocation.cs @@ -59,7 +59,7 @@ public enum RelocType // Windows arm64 TLS access IMAGE_REL_ARM64_TLS_SECREL_HIGH12A = 0x10F, // ADD high 12-bit offset for tls - IMAGE_REL_ARM64_TLS_SECREL_LOW12L = 0x110, // ADD low 12-bit offset for tls + IMAGE_REL_ARM64_TLS_SECREL_LOW12A = 0x110, // ADD low 12-bit offset for tls // // Relocations for R2R image production @@ -536,7 +536,7 @@ public static unsafe void WriteValue(RelocType relocType, void* location, long v break; case RelocType.IMAGE_REL_BASED_ARM64_PAGEOFFSET_12A: case RelocType.IMAGE_REL_AARCH64_TLSDESC_ADD_LO12: - case RelocType.IMAGE_REL_ARM64_TLS_SECREL_LOW12L: + case RelocType.IMAGE_REL_ARM64_TLS_SECREL_LOW12A: PutArm64Rel12((uint*)location, (int)value); break; case RelocType.IMAGE_REL_BASED_LOONGARCH64_PC: @@ -593,7 +593,7 @@ public static unsafe long ReadValue(RelocType relocType, void* location) return GetArm64Rel21((uint*)location); case RelocType.IMAGE_REL_BASED_ARM64_PAGEOFFSET_12A: case RelocType.IMAGE_REL_ARM64_TLS_SECREL_HIGH12A: - case RelocType.IMAGE_REL_ARM64_TLS_SECREL_LOW12L: + case RelocType.IMAGE_REL_ARM64_TLS_SECREL_LOW12A: return GetArm64Rel12((uint*)location); case RelocType.IMAGE_REL_AARCH64_TLSDESC_LD64_LO12: case RelocType.IMAGE_REL_AARCH64_TLSDESC_ADD_LO12: diff --git a/src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs b/src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs index c97828d4f01d53..fccc5427ce5c8f 100644 --- a/src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs +++ b/src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs @@ -3909,8 +3909,8 @@ private static RelocType GetRelocType(TargetArchitecture targetArchitecture, ush const ushort IMAGE_REL_ARM64_BRANCH26 = 3; const ushort IMAGE_REL_ARM64_PAGEBASE_REL21 = 4; const ushort IMAGE_REL_ARM64_PAGEOFFSET_12A = 6; + const ushort IMAGE_REL_ARM64_SECREL_LOW12A = 9; const ushort IMAGE_REL_ARM64_SECREL_HIGH12A = 0xA; - const ushort IMAGE_REL_ARM64_SECREL_LOW12L = 0xB; const ushort IMAGE_REL_ARM64_TLSDESC_ADR_PAGE21 = 0x107; const ushort IMAGE_REL_ARM64_TLSDESC_LD64_LO12 = 0x108; const ushort IMAGE_REL_ARM64_TLSDESC_ADD_LO12 = 0x109; @@ -3935,8 +3935,8 @@ private static RelocType GetRelocType(TargetArchitecture targetArchitecture, ush return RelocType.IMAGE_REL_AARCH64_TLSDESC_CALL; case IMAGE_REL_ARM64_SECREL_HIGH12A: return RelocType.IMAGE_REL_ARM64_TLS_SECREL_HIGH12A; - case IMAGE_REL_ARM64_SECREL_LOW12L: - return RelocType.IMAGE_REL_ARM64_TLS_SECREL_LOW12L; + case IMAGE_REL_ARM64_SECREL_LOW12A: + return RelocType.IMAGE_REL_ARM64_TLS_SECREL_LOW12A; default: Debug.Fail("Invalid RelocType: " + fRelocType); return 0; diff --git a/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/ObjectWriter/CoffObjectWriter.cs b/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/ObjectWriter/CoffObjectWriter.cs index 3660c16daf4827..d6deb27606a4a1 100644 --- a/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/ObjectWriter/CoffObjectWriter.cs +++ b/src/coreclr/tools/aot/ILCompiler.Compiler/Compiler/ObjectWriter/CoffObjectWriter.cs @@ -355,7 +355,7 @@ private protected override void EmitRelocations(int sectionIndex, List IMAGE_REL_ARM64_PAGEBASE_REL21, IMAGE_REL_BASED_ARM64_PAGEOFFSET_12A => IMAGE_REL_ARM64_PAGEOFFSET_12A, IMAGE_REL_ARM64_TLS_SECREL_HIGH12A => IMAGE_REL_ARM64_SECREL_HIGH12A, - IMAGE_REL_ARM64_TLS_SECREL_LOW12L => IMAGE_REL_ARM64_SECREL_LOW12L, + IMAGE_REL_ARM64_TLS_SECREL_LOW12A => IMAGE_REL_ARM64_SECREL_LOW12A, IMAGE_REL_SECREL => IMAGE_REL_ARM64_SECREL, IMAGE_REL_SECTION => IMAGE_REL_ARM64_SECTION, _ => throw new NotSupportedException($"Unsupported relocation: {relocation.Type}") diff --git a/src/coreclr/tools/superpmi/superpmi-shared/compileresult.cpp b/src/coreclr/tools/superpmi/superpmi-shared/compileresult.cpp index 74040dc5aa3bef..e2087690ac3f2c 100644 --- a/src/coreclr/tools/superpmi/superpmi-shared/compileresult.cpp +++ b/src/coreclr/tools/superpmi/superpmi-shared/compileresult.cpp @@ -888,6 +888,8 @@ void CompileResult::applyRelocs(RelocContext* rc, unsigned char* block1, ULONG b } break; + case IMAGE_REL_ARM64_SECREL_HIGH12A: + case IMAGE_REL_ARM64_SECREL_LOW12A: case IMAGE_REL_AARCH64_TLSDESC_LD64_LO12: case IMAGE_REL_AARCH64_TLSDESC_ADD_LO12: // TLSDESC ADD for corresponding ADRP case IMAGE_REL_AARCH64_TLSDESC_CALL: From 55a4abf7ea848447e2a43d4319cdfd1836e49e8f Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Tue, 16 Jul 2024 13:56:27 -0700 Subject: [PATCH 02/10] do not track tls_index reference --- src/coreclr/jit/helperexpansion.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/coreclr/jit/helperexpansion.cpp b/src/coreclr/jit/helperexpansion.cpp index 739edf207f6c5d..6e8675234cfd4f 100644 --- a/src/coreclr/jit/helperexpansion.cpp +++ b/src/coreclr/jit/helperexpansion.cpp @@ -595,7 +595,10 @@ bool Compiler::fgExpandThreadLocalAccessForCallNativeAOT(BasicBlock** pBlock, St CORINFO_CONST_LOOKUP tlsIndexObject = threadStaticInfo.tlsIndexObject; + // We want tls_index to get relocated and hence create IconHandle node, + // but it does not have GC ref, so reset the type to TYP_I_IMPL instead of TYP_REF GenTree* dllRef = gtNewIconHandleNode((size_t)tlsIndexObject.handle, GTF_ICON_OBJ_HDL); + dllRef->gtType = TYP_I_IMPL; dllRef = gtNewIndir(TYP_INT, dllRef, GTF_IND_NONFAULTING | GTF_IND_INVARIANT); dllRef = gtNewCastNode(TYP_I_IMPL, dllRef, true, TYP_I_IMPL); dllRef = gtNewOperNode(GT_LSH, TYP_I_IMPL, dllRef, gtNewIconNode(3, TYP_I_IMPL)); From fc429980e8cdb01806dddddabdc9096bc8c1b8d8 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Tue, 16 Jul 2024 14:37:00 -0700 Subject: [PATCH 03/10] Update guid so the new collection contains correct reloc data --- src/coreclr/inc/jiteeversionguid.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/coreclr/inc/jiteeversionguid.h b/src/coreclr/inc/jiteeversionguid.h index 84284fd2c34a7b..a6ad06fade3389 100644 --- a/src/coreclr/inc/jiteeversionguid.h +++ b/src/coreclr/inc/jiteeversionguid.h @@ -43,11 +43,11 @@ typedef const GUID *LPCGUID; #define GUID_DEFINED #endif // !GUID_DEFINED -constexpr GUID JITEEVersionIdentifier = { /* e6c7a441-8d3c-4135-abc2-bc4dd7c6a4d7 */ - 0xe6c7a441, - 0x8d3c, - 0x4135, - {0xab, 0xc2, 0xbc, 0x4d, 0xd7, 0xc6, 0xa4, 0xd7} +constexpr GUID JITEEVersionIdentifier = { /* 488a17ce-26c9-4ad0-a7b7-79bf320ea4d1 */ + 0x488a17ce, + 0x26c9, + 0x4ad0, + {0xa7, 0xb7, 0x79, 0xbf, 0x32, 0x0e, 0xa4, 0xd1} }; ////////////////////////////////////////////////////////////////////////////////////////////////////////// From f54bd5c4ed009cb0a86854b1c3b2c9c8fd8b9885 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 17 Jul 2024 20:20:33 -0700 Subject: [PATCH 04/10] fix the code for Add --- src/coreclr/jit/codegenarm64.cpp | 11 +++++++++++ src/coreclr/jit/emitarm64.cpp | 23 +++++++++++++++++++++-- src/coreclr/jit/helperexpansion.cpp | 5 +++++ 3 files changed, 37 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 2f6ebaf56fc841..90adf314665dd2 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2764,6 +2764,17 @@ void CodeGen::genCodeForBinary(GenTreeOp* tree) genProduceReg(tree); return; } + else if (compiler->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsWindows && op2->IsIconHandle(GTF_ICON_SECREL_OFFSET)) + { + // This is the Add needed for TLS/windows/arm64 + assert(op2->AsIntCon()->ImmedValNeedsReloc(compiler)); + + emitAttr attr = emitActualTypeSize(targetType); + attr = EA_SET_FLG(attr, EA_CNS_RELOC_FLG | EA_CNS_SEC_RELOC); + + emit->emitIns_Add_Add_Tls_Reloc(attr, targetReg, op2->AsIntCon()->IconValue()); + return; + } instruction ins = genGetInsForOper(tree->OperGet(), targetType); diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index dea329b38ab1b2..7c6da8f99a5b0b 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -13539,13 +13539,32 @@ void emitter::emitDispInsHelp( if (id->idIsReloc()) { assert(ins == INS_add); - printf("[LOW RELOC "); + + if (emitComp->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsWindows && id->idIsTlsGD()) + { + printf("[HIGH RELOC "); + } + else + { + printf("[LOW RELOC "); + } + emitDispImm((ssize_t)id->idAddr()->iiaAddr, false); printf("]"); } else { - emitDispImmOptsLSL(emitGetInsSC(id), insOptsLSL12(id->idInsOpt()), 12); + if (emitComp->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsWindows && id->idIsTlsGD()) + { + assert(ins == INS_add); + printf("[LOW RELOC "); + emitDispImmOptsLSL(emitGetInsSC(id), insOptsLSL12(id->idInsOpt()), 12); + printf("]"); + } + else + { + emitDispImmOptsLSL(emitGetInsSC(id), insOptsLSL12(id->idInsOpt()), 12); + } } break; diff --git a/src/coreclr/jit/helperexpansion.cpp b/src/coreclr/jit/helperexpansion.cpp index 6e8675234cfd4f..3ba520b5665676 100644 --- a/src/coreclr/jit/helperexpansion.cpp +++ b/src/coreclr/jit/helperexpansion.cpp @@ -613,6 +613,11 @@ bool Compiler::fgExpandThreadLocalAccessForCallNativeAOT(BasicBlock** pBlock, St GenTree* tlsRootOffset = gtNewIconNode((size_t)tlsRootObject, TYP_INT); tlsRootOffset->gtFlags |= GTF_ICON_SECREL_OFFSET; + if (TargetArchitecture::IsArm64) + { + tlsRootOffset->SetContained(); + } + // Add the tlsValue and tlsRootOffset to produce tlsRootAddr. tlsRootAddr = gtNewOperNode(GT_ADD, TYP_I_IMPL, tlsValue, tlsRootOffset); } From 5732da812121fc985d7a783a8735d81c4e023742 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 17 Jul 2024 20:38:35 -0700 Subject: [PATCH 05/10] remove old code and add comment --- src/coreclr/jit/codegenarm64.cpp | 10 ++-------- src/coreclr/jit/helperexpansion.cpp | 3 +++ 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 90adf314665dd2..4f7bd68c140730 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2236,18 +2236,12 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr size, // reg cannot be a FP register assert(!genIsValidFloatReg(reg)); - emitAttr origAttr = size; if (!compiler->opts.compReloc) { size = EA_SIZE(size); // Strip any Reloc flags from size if we aren't doing relocs } - if (compiler->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && EA_IS_CNS_SEC_RELOC(origAttr)) - { - // This emits pair of `add` instructions for TLS reloc - GetEmitter()->emitIns_Add_Add_Tls_Reloc(size, reg, imm DEBUGARG(gtFlags)); - } - else if (EA_IS_RELOC(size)) + if (EA_IS_RELOC(size)) { // This emits a pair of adrp/add (two instructions) with fix-ups. GetEmitter()->emitIns_R_AI(INS_adrp, size, reg, imm DEBUGARG(targetHandle) DEBUGARG(gtFlags)); @@ -2766,7 +2760,7 @@ void CodeGen::genCodeForBinary(GenTreeOp* tree) } else if (compiler->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsWindows && op2->IsIconHandle(GTF_ICON_SECREL_OFFSET)) { - // This is the Add needed for TLS/windows/arm64 + // This emits pair of `add` instructions for TLS reloc on windows/arm64/nativeaot assert(op2->AsIntCon()->ImmedValNeedsReloc(compiler)); emitAttr attr = emitActualTypeSize(targetType); diff --git a/src/coreclr/jit/helperexpansion.cpp b/src/coreclr/jit/helperexpansion.cpp index 3ba520b5665676..8444b0b17eb492 100644 --- a/src/coreclr/jit/helperexpansion.cpp +++ b/src/coreclr/jit/helperexpansion.cpp @@ -615,6 +615,9 @@ bool Compiler::fgExpandThreadLocalAccessForCallNativeAOT(BasicBlock** pBlock, St if (TargetArchitecture::IsArm64) { + // for windows/arm64, the immediate constant should be contained because it gets + // generated as part of ADD instruction that consumes this constant. See + // emitIns_Add_Add_Tls_Reloc(). tlsRootOffset->SetContained(); } From 87561d8c9b0d421158dcf6f53d010de1bcaed37b Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Wed, 17 Jul 2024 20:40:41 -0700 Subject: [PATCH 06/10] jit format --- src/coreclr/jit/codegenarm64.cpp | 5 +++-- src/coreclr/jit/emitarm64.cpp | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 4f7bd68c140730..8b8082cad5fff8 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2758,12 +2758,13 @@ void CodeGen::genCodeForBinary(GenTreeOp* tree) genProduceReg(tree); return; } - else if (compiler->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsWindows && op2->IsIconHandle(GTF_ICON_SECREL_OFFSET)) + else if (compiler->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsWindows && + op2->IsIconHandle(GTF_ICON_SECREL_OFFSET)) { // This emits pair of `add` instructions for TLS reloc on windows/arm64/nativeaot assert(op2->AsIntCon()->ImmedValNeedsReloc(compiler)); - emitAttr attr = emitActualTypeSize(targetType); + emitAttr attr = emitActualTypeSize(targetType); attr = EA_SET_FLG(attr, EA_CNS_RELOC_FLG | EA_CNS_SEC_RELOC); emit->emitIns_Add_Add_Tls_Reloc(attr, targetReg, op2->AsIntCon()->IconValue()); diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 7c6da8f99a5b0b..c0ce78d8dd0b2b 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -13548,7 +13548,7 @@ void emitter::emitDispInsHelp( { printf("[LOW RELOC "); } - + emitDispImm((ssize_t)id->idAddr()->iiaAddr, false); printf("]"); } From 74e65c67993bbee45f8717e6595bb32c36075f04 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Thu, 18 Jul 2024 10:27:27 -0700 Subject: [PATCH 07/10] Add Arm64 target in reproNative.vcxproj --- src/coreclr/jit/codegenarm64.cpp | 2 +- src/coreclr/jit/emitarm64.cpp | 7 +- src/coreclr/jit/emitarm64.h | 2 +- .../reproNative/reproNative.vcxproj | 113 +++++++++++++++++- 4 files changed, 118 insertions(+), 6 deletions(-) diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 8b8082cad5fff8..2ac66ba5ea7770 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -2767,7 +2767,7 @@ void CodeGen::genCodeForBinary(GenTreeOp* tree) emitAttr attr = emitActualTypeSize(targetType); attr = EA_SET_FLG(attr, EA_CNS_RELOC_FLG | EA_CNS_SEC_RELOC); - emit->emitIns_Add_Add_Tls_Reloc(attr, targetReg, op2->AsIntCon()->IconValue()); + emit->emitIns_Add_Add_Tls_Reloc(attr, targetReg, op1->GetRegNum(), op2->AsIntCon()->IconValue()); return; } diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index c0ce78d8dd0b2b..382f71f6a9e7a8 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -3756,6 +3756,7 @@ void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg, insOpts o // gtFlags - DEBUG only gtFlags. // void emitter::emitIns_Add_Add_Tls_Reloc(emitAttr attr, + regNumber targetReg, regNumber reg, ssize_t imm DEBUGARG(GenTreeFlags gtFlags /* = GTF_EMPTY */)) { @@ -3777,7 +3778,7 @@ void emitter::emitIns_Add_Add_Tls_Reloc(emitAttr attr, id->idInsOpt(INS_OPTS_LSL12); id->idAddr()->iiaAddr = (BYTE*)imm; - id->idReg1(reg); + id->idReg1(targetReg); id->idReg2(reg); // Since this is relocation, set to 8 byte size. @@ -3804,7 +3805,7 @@ void emitter::emitIns_Add_Add_Tls_Reloc(emitAttr attr, id->idInsFmt(fmt); id->idAddr()->iiaAddr = (BYTE*)imm; - id->idReg1(reg); + id->idReg1(targetReg); id->idReg2(reg); // Since this is relocation, set to 8 byte size. @@ -13558,7 +13559,7 @@ void emitter::emitDispInsHelp( { assert(ins == INS_add); printf("[LOW RELOC "); - emitDispImmOptsLSL(emitGetInsSC(id), insOptsLSL12(id->idInsOpt()), 12); + emitDispImm((ssize_t)id->idAddr()->iiaAddr, false); printf("]"); } else diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 4629923358d189..d5de8728483466 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -1455,7 +1455,7 @@ void emitIns_R_I(instruction ins, insOpts opt = INS_OPTS_NONE, insScalableOpts sopt = INS_SCALABLE_OPTS_NONE DEBUGARG(size_t targetHandle = 0) DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY)); -void emitIns_Add_Add_Tls_Reloc(emitAttr attr, regNumber reg, ssize_t imm DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY)); +void emitIns_Add_Add_Tls_Reloc(emitAttr attr, regNumber targetReg, regNumber reg, ssize_t imm DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY)); void emitInsSve_R_I(instruction ins, emitAttr attr, diff --git a/src/coreclr/tools/aot/ILCompiler/reproNative/reproNative.vcxproj b/src/coreclr/tools/aot/ILCompiler/reproNative/reproNative.vcxproj index 5a94961e04926e..d0e08605427a3a 100644 --- a/src/coreclr/tools/aot/ILCompiler/reproNative/reproNative.vcxproj +++ b/src/coreclr/tools/aot/ILCompiler/reproNative/reproNative.vcxproj @@ -1,9 +1,17 @@ + + Checked + ARM64 + Checked Win32 + + Debug + ARM64 + Debug Win32 @@ -16,6 +24,10 @@ Checked x64 + + Release + ARM64 + Release Win32 @@ -42,6 +54,12 @@ v143 Unicode + + Application + true + v143 + Unicode + Application true @@ -55,6 +73,13 @@ true Unicode + + Application + false + v143 + true + Unicode + Application false @@ -69,6 +94,13 @@ true Unicode + + Application + false + v143 + true + Unicode + Application false @@ -82,18 +114,27 @@ + + + + + + + + + @@ -102,6 +143,10 @@ false false + + false + false + false false @@ -110,6 +155,10 @@ false false + + false + false + false false @@ -118,6 +167,10 @@ false false + + false + false + false false @@ -140,6 +193,24 @@ $(ArtifactsRoot)bin\repro\x64\Debug\repro.obj;$(Win32SDKLibs);%(AdditionalDependencies);$(ArtifactsRoot)bin\coreclr\windows.x64.Debug\aotsdk\Runtime.WorkstationGC.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Debug\aotsdk\System.Globalization.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Debug\aotsdk\System.IO.Compression.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Debug\aotsdk\eventpipe-disabled.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Debug\aotsdk\Runtime.VxsortDisabled.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Debug\aotsdk\standalonegc-disabled.lib + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;_LIB;HOST_ARM64;%(PreprocessorDefinitions) + true + $(CoreClrSourceRoot)gc;$(CoreClrSourceRoot)gc\env + 4477 + MultiThreadedDebug + false + ProgramDatabase + + + Console + true + $(ArtifactsRoot)bin\repro\Arm64\Debug\repro.obj;$(Win32SDKLibs);%(AdditionalDependencies);$(ArtifactsRoot)bin\coreclr\windows.Arm64.Debug\aotsdk\Runtime.WorkstationGC.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Debug\aotsdk\System.Globalization.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Debug\aotsdk\System.IO.Compression.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Debug\aotsdk\eventpipe-disabled.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Debug\aotsdk\standalonegc-disabled.lib + + Level3 @@ -179,6 +250,26 @@ $(ArtifactsRoot)bin\repro\x64\Checked\repro.obj;$(Win32SDKLibs);%(AdditionalDependencies);$(ArtifactsRoot)bin\coreclr\windows.x64.Checked\aotsdk\Runtime.WorkstationGC.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Checked\aotsdk\System.Globalization.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Checked\aotsdk\System.IO.Compression.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Checked\aotsdk\eventpipe-disabled.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Checked\aotsdk\Runtime.VxsortDisabled.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Checked\aotsdk\standalonegc-disabled.lib + + + Level3 + MaxSpeed + true + true + _DEBUG;_CONSOLE;_LIB;HOST_ARM64;%(PreprocessorDefinitions) + true + $(CoreClrSourceRoot)gc;$(CoreClrSourceRoot)gc\env + 4477 + MultiThreadedDebug + + + Console + true + true + true + $(ArtifactsRoot)bin\repro\Arm64\Checked\repro.obj;$(Win32SDKLibs);%(AdditionalDependencies);$(ArtifactsRoot)bin\coreclr\windows.Arm64.Checked\aotsdk\Runtime.WorkstationGC.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Checked\aotsdk\System.Globalization.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Checked\aotsdk\System.IO.Compression.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Checked\aotsdk\eventpipe-disabled.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Checked\aotsdk\standalonegc-disabled.lib + + Level3 @@ -220,6 +311,26 @@ $(ArtifactsRoot)bin\repro\x64\Release\repro.obj;$(Win32SDKLibs);%(AdditionalDependencies);$(ArtifactsRoot)bin\coreclr\windows.x64.Release\aotsdk\Runtime.WorkstationGC.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Release\aotsdk\System.Globalization.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Release\aotsdk\System.IO.Compression.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Release\aotsdk\eventpipe-disabled.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Release\aotsdk\Runtime.VxsortDisabled.lib;$(ArtifactsRoot)bin\coreclr\windows.x64.Release\aotsdk\standalonegc-disabled.lib + + + Level3 + MaxSpeed + true + true + NDEBUG;_CONSOLE;_LIB;HOST_ARM64;%(PreprocessorDefinitions) + true + $(CoreClrSourceRoot)gc;$(CoreClrSourceRoot)gc\env + 4477 + MultiThreaded + + + Console + true + true + true + $(ArtifactsRoot)bin\repro\Arm64\Release\repro.obj;$(Win32SDKLibs);%(AdditionalDependencies);$(ArtifactsRoot)bin\coreclr\windows.Arm64.Release\aotsdk\Runtime.WorkstationGC.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Release\aotsdk\System.Globalization.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Release\aotsdk\System.IO.Compression.Native.Aot.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Release\aotsdk\eventpipe-disabled.lib;$(ArtifactsRoot)bin\coreclr\windows.Arm64.Release\aotsdk\standalonegc-disabled.lib + + Level3 @@ -252,4 +363,4 @@ - + \ No newline at end of file From eb5c691450be28db52af2e8ca51243e0a9a6504a Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Thu, 18 Jul 2024 11:45:14 -0700 Subject: [PATCH 08/10] jit format --- src/coreclr/jit/emitarm64.cpp | 2 +- src/coreclr/jit/emitarm64.h | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 382f71f6a9e7a8..f831e0aa1b6915 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -3756,7 +3756,7 @@ void emitter::emitIns_R(instruction ins, emitAttr attr, regNumber reg, insOpts o // gtFlags - DEBUG only gtFlags. // void emitter::emitIns_Add_Add_Tls_Reloc(emitAttr attr, - regNumber targetReg, + regNumber targetReg, regNumber reg, ssize_t imm DEBUGARG(GenTreeFlags gtFlags /* = GTF_EMPTY */)) { diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index d5de8728483466..1aeeb46942e5f1 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -1455,7 +1455,10 @@ void emitIns_R_I(instruction ins, insOpts opt = INS_OPTS_NONE, insScalableOpts sopt = INS_SCALABLE_OPTS_NONE DEBUGARG(size_t targetHandle = 0) DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY)); -void emitIns_Add_Add_Tls_Reloc(emitAttr attr, regNumber targetReg, regNumber reg, ssize_t imm DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY)); +void emitIns_Add_Add_Tls_Reloc(emitAttr attr, + regNumber targetReg, + regNumber reg, + ssize_t imm DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY)); void emitInsSve_R_I(instruction ins, emitAttr attr, From b1bd5e06a39678f649c40f10d1a44e9ea74caf42 Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Thu, 18 Jul 2024 22:20:04 -0700 Subject: [PATCH 09/10] review feedback --- src/coreclr/jit/helperexpansion.cpp | 13 +------------ src/coreclr/jit/lowerarmarch.cpp | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/src/coreclr/jit/helperexpansion.cpp b/src/coreclr/jit/helperexpansion.cpp index 8444b0b17eb492..1580a3fbba362e 100644 --- a/src/coreclr/jit/helperexpansion.cpp +++ b/src/coreclr/jit/helperexpansion.cpp @@ -595,10 +595,7 @@ bool Compiler::fgExpandThreadLocalAccessForCallNativeAOT(BasicBlock** pBlock, St CORINFO_CONST_LOOKUP tlsIndexObject = threadStaticInfo.tlsIndexObject; - // We want tls_index to get relocated and hence create IconHandle node, - // but it does not have GC ref, so reset the type to TYP_I_IMPL instead of TYP_REF - GenTree* dllRef = gtNewIconHandleNode((size_t)tlsIndexObject.handle, GTF_ICON_OBJ_HDL); - dllRef->gtType = TYP_I_IMPL; + GenTree* dllRef = gtNewIconHandleNode((size_t)tlsIndexObject.handle, GTF_ICON_CONST_PTR); dllRef = gtNewIndir(TYP_INT, dllRef, GTF_IND_NONFAULTING | GTF_IND_INVARIANT); dllRef = gtNewCastNode(TYP_I_IMPL, dllRef, true, TYP_I_IMPL); dllRef = gtNewOperNode(GT_LSH, TYP_I_IMPL, dllRef, gtNewIconNode(3, TYP_I_IMPL)); @@ -613,14 +610,6 @@ bool Compiler::fgExpandThreadLocalAccessForCallNativeAOT(BasicBlock** pBlock, St GenTree* tlsRootOffset = gtNewIconNode((size_t)tlsRootObject, TYP_INT); tlsRootOffset->gtFlags |= GTF_ICON_SECREL_OFFSET; - if (TargetArchitecture::IsArm64) - { - // for windows/arm64, the immediate constant should be contained because it gets - // generated as part of ADD instruction that consumes this constant. See - // emitIns_Add_Add_Tls_Reloc(). - tlsRootOffset->SetContained(); - } - // Add the tlsValue and tlsRootOffset to produce tlsRootAddr. tlsRootAddr = gtNewOperNode(GT_ADD, TYP_I_IMPL, tlsValue, tlsRootOffset); } diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index cd5032921804d2..9daa7fe2e7dbbf 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -68,7 +68,21 @@ bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const if (!childNode->IsCnsIntOrI()) return false; if (childNode->AsIntCon()->ImmedValNeedsReloc(comp)) - return false; + { + if (comp->IsTargetAbi(CORINFO_NATIVEAOT_ABI) && TargetOS::IsWindows && + childNode->IsIconHandle(GTF_ICON_SECREL_OFFSET)) + { + // for windows/arm64, the immediate constant should be contained because it gets + // generated as part of ADD instruction that consumes this constant. See + // emitIns_Add_Add_Tls_Reloc(). + return true; + } + else + { + return false; + } + } + // TODO-CrossBitness: we wouldn't need the cast below if GenTreeIntCon::gtIconVal had target_ssize_t type. target_ssize_t immVal = (target_ssize_t)childNode->AsIntCon()->gtIconVal; From 7d2f70c1ccb86fdcdaf7854e60aeb69122f412ec Mon Sep 17 00:00:00 2001 From: Kunal Pathak Date: Fri, 19 Jul 2024 06:59:52 -0700 Subject: [PATCH 10/10] jit format --- src/coreclr/jit/lowerarmarch.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index 9daa7fe2e7dbbf..855c4f21917e50 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -80,9 +80,8 @@ bool Lowering::IsContainableImmed(GenTree* parentNode, GenTree* childNode) const else { return false; - } + } } - // TODO-CrossBitness: we wouldn't need the cast below if GenTreeIntCon::gtIconVal had target_ssize_t type. target_ssize_t immVal = (target_ssize_t)childNode->AsIntCon()->gtIconVal;