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clamp03clamp03
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[RISC-V][JIT] Fix branch
1 parent 51d467a commit a400b3e

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3 files changed

+34
-16
lines changed

3 files changed

+34
-16
lines changed

‎src/coreclr/jit/emitriscv64.cpp‎

Lines changed: 18 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -667,6 +667,7 @@ void emitter::emitIns_R_R_I(
667667
{
668668
assert(isGeneralRegister(reg1));
669669
assert(isGeneralRegister(reg2));
670+
assert(isValidSimm13(imm));
670671
code |= reg1 << 15;
671672
code |= reg2 << 20;
672673
code |= ((imm >> 11) & 0x1) << 7;
@@ -1621,10 +1622,10 @@ void emitter::emitJumpDistBind()
16211622
#endif // DEBUG
16221623

16231624
// NOTE:
1624-
// bit0 of isLinkingEnd_LA: indicating whether updating the instrDescJmp's size with the type INS_OPTS_J;
1625-
// bit1 of isLinkingEnd_LA: indicating not needed updating the size while emitTotalCodeSize <= (0x7fff << 2) or had
1625+
// bit0 of isLinkingEnd: indicating whether updating the instrDescJmp's size with the type INS_OPTS_J;
1626+
// bit1 of isLinkingEnd: indicating not needed updating the size while emitTotalCodeSize <= 0xfff or had
16261627
// updated;
1627-
unsigned int isLinkingEnd_LA = emitTotalCodeSize <= (0x7fff << 2) ? 2 : 0;
1628+
unsigned int isLinkingEnd = emitTotalCodeSize <= 0xfff ? 2 : 0;
16281629

16291630
UNATIVE_OFFSET ssz = 0; // relative small jump's delay-slot.
16301631
// small jump max. neg distance
@@ -1836,7 +1837,7 @@ void emitter::emitJumpDistBind()
18361837
assert(jmpDist >= 0); // Forward jump
18371838
assert(!(jmpDist & 0x3));
18381839

1839-
if (isLinkingEnd_LA & 0x2)
1840+
if (isLinkingEnd & 0x2)
18401841
{
18411842
jmp->idAddr()->iiaSetJmpOffset(jmpDist);
18421843
}
@@ -1879,7 +1880,7 @@ void emitter::emitJumpDistBind()
18791880
adjIG += (UNATIVE_OFFSET)extra;
18801881
emitTotalCodeSize += (UNATIVE_OFFSET)extra;
18811882
jmpIG->igFlags |= IGF_UPD_ISZ;
1882-
isLinkingEnd_LA |= 0x1;
1883+
isLinkingEnd |= 0x1;
18831884
}
18841885
continue;
18851886
}
@@ -1923,7 +1924,7 @@ void emitter::emitJumpDistBind()
19231924
assert(jmpDist >= 0); // Backward jump
19241925
assert(!(jmpDist & 0x3));
19251926

1926-
if (isLinkingEnd_LA & 0x2)
1927+
if (isLinkingEnd & 0x2)
19271928
{
19281929
jmp->idAddr()->iiaSetJmpOffset(-jmpDist); // Backward jump is negative!
19291930
}
@@ -1954,7 +1955,7 @@ void emitter::emitJumpDistBind()
19541955
}
19551956
else
19561957
{
1957-
assert(ins == INS_jal || ins == INS_jalr);
1958+
assert(ins == INS_jal || ins == INS_jalr || ins == INS_j);
19581959
assert((jmpDist + emitCounts_INS_OPTS_J * 4) < 0x8000000);
19591960
continue;
19601961
}
@@ -1966,17 +1967,17 @@ void emitter::emitJumpDistBind()
19661967
adjIG += (UNATIVE_OFFSET)extra;
19671968
emitTotalCodeSize += (UNATIVE_OFFSET)extra;
19681969
jmpIG->igFlags |= IGF_UPD_ISZ;
1969-
isLinkingEnd_LA |= 0x1;
1970+
isLinkingEnd |= 0x1;
19701971
}
19711972
continue;
19721973
}
19731974
} // end for each jump
19741975

1975-
if ((isLinkingEnd_LA & 0x3) < 0x2)
1976+
if ((isLinkingEnd & 0x3) < 0x2)
19761977
{
19771978
// indicating the instrDescJmp's size of the type INS_OPTS_J had updated
19781979
// after the first round and should iterate again to update.
1979-
isLinkingEnd_LA = 0x2;
1980+
isLinkingEnd = 0x2;
19801981

19811982
// Adjust offsets of any remaining blocks.
19821983
for (; lstIG;)
@@ -2460,7 +2461,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
24602461
}
24612462
else
24622463
{
2463-
assert((-0x100000 <= imm) && (imm < 0x100000));
2464+
assert(isValidSimm21(imm));
24642465
assert((emitInsCode(INS_bne) & 0xefff) == emitInsCode(INS_beq));
24652466

24662467
code = emitInsCode(ins) ^ 0x1000;
@@ -2482,7 +2483,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
24822483
}
24832484
else if ((INS_blt <= ins) && (ins <= INS_bgeu))
24842485
{
2485-
assert((-0x100000 <= imm) && (imm < 0x100000));
2486+
assert(isValidSimm21(imm));
24862487
assert((emitInsCode(INS_bge) & 0xefff) == emitInsCode(INS_blt));
24872488
assert((emitInsCode(INS_bgeu) & 0xefff) == emitInsCode(INS_bltu));
24882489

@@ -2542,6 +2543,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
25422543
code = emitInsCode(ins);
25432544
if (ins == INS_jal)
25442545
{
2546+
assert(isValidSimm21(imm));
25452547
code |= ((imm >> 12) & 0xff) << 12;
25462548
code |= ((imm >> 11) & 0x1) << 20;
25472549
code |= ((imm >> 1) & 0x3ff) << 21;
@@ -2550,17 +2552,20 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
25502552
}
25512553
else if (ins == INS_j)
25522554
{
2555+
assert(isValidSimm21(imm));
25532556
code |= ((imm >> 12) & 0xff) << 12;
25542557
code |= ((imm >> 11) & 0x1) << 20;
25552558
code |= ((imm >> 1) & 0x3ff) << 21;
25562559
code |= ((imm >> 20) & 0x1) << 31;
25572560
}
25582561
else if (ins == INS_jalr)
25592562
{
2563+
assert(isValidSimm12(imm));
25602564
code |= ((code_t)(imm & 0xfff) << 20);
25612565
}
25622566
else if (ins == INS_bnez || ins == INS_beqz)
25632567
{
2568+
assert(isValidSimm13(imm));
25642569
code |= (code_t)id->idReg1() << 15;
25652570
code |= ((imm >> 11) & 0x1) << 7;
25662571
code |= ((imm >> 1) & 0xf) << 8;
@@ -2569,6 +2574,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
25692574
}
25702575
else if ((INS_beq <= ins) && (ins <= INS_bgeu))
25712576
{
2577+
assert(isValidSimm13(imm));
25722578
code |= ((code_t)id->idReg1()) << 15;
25732579
code |= ((code_t)id->idReg2()) << 20;
25742580
code |= ((imm >> 11) & 0x1) << 7;

‎src/coreclr/jit/emitriscv64.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,12 @@ bool IsRedundantLdStr(
8181
/************************************************************************/
8282

8383
public:
84+
// Returns true if 'value' is a legal signed immediate 13 bit encoding.
85+
static bool isValidSimm13(ssize_t value)
86+
{
87+
return -(((int)1) << 12) <= value && value < (((int)1) << 12);
88+
};
89+
8490
// Returns true if 'value' is a legal signed immediate 12 bit encoding.
8591
static bool isValidSimm12(ssize_t value)
8692
{
@@ -105,6 +111,12 @@ static bool isValidSimm20(ssize_t value)
105111
return -(((int)1) << 19) <= value && value < (((int)1) << 19);
106112
};
107113

114+
// Returns true if 'value' is a legal signed immediate 21 bit encoding.
115+
static bool isValidSimm21(ssize_t value)
116+
{
117+
return -(((int)1) << 20) <= value && value < (((int)1) << 20);
118+
};
119+
108120
// Returns true if 'value' is a legal signed immediate 32 bit encoding.
109121
static bool isValidSimm32(ssize_t value)
110122
{

‎src/coreclr/jit/targetriscv64.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -295,11 +295,11 @@
295295
extern const regNumber fltArgRegs [MAX_FLOAT_REG_ARG];
296296
extern const regMaskTP fltArgMasks[MAX_FLOAT_REG_ARG];
297297

298-
#define B_DIST_SMALL_MAX_NEG (-131072)
299-
#define B_DIST_SMALL_MAX_POS (+131071)
298+
#define B_DIST_SMALL_MAX_NEG (-4096)
299+
#define B_DIST_SMALL_MAX_POS (+4095)
300300

301-
#define OFFSET_DIST_SMALL_MAX_NEG (-2048)
302-
#define OFFSET_DIST_SMALL_MAX_POS (+2047)
301+
#define OFFSET_DIST_SMALL_MAX_NEG (-1048)
302+
#define OFFSET_DIST_SMALL_MAX_POS (+1047)
303303

304304
#define STACK_PROBE_BOUNDARY_THRESHOLD_BYTES 0
305305

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