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SVE2 API for FusedAddHalving and FusedSubtractHalving (#117609)
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‎src/coreclr/jit/hwintrinsiclistarm64sve.h‎

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Original file line numberDiff line numberDiff line change
@@ -337,6 +337,8 @@ HARDWARE_INTRINSIC(Sve2, BitwiseClearXor,
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HARDWARE_INTRINSIC(Sve2, BitwiseSelect, -1, 3, {INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
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HARDWARE_INTRINSIC(Sve2, BitwiseSelectLeftInverted, -1, 3, {INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
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HARDWARE_INTRINSIC(Sve2, BitwiseSelectRightInverted, -1, 3, {INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics)
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HARDWARE_INTRINSIC(Sve2, FusedAddHalving, -1, -1, {INS_sve_shadd, INS_sve_uhadd, INS_sve_shadd, INS_sve_uhadd, INS_sve_shadd, INS_sve_uhadd, INS_sve_shadd, INS_sve_uhadd, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
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HARDWARE_INTRINSIC(Sve2, FusedSubtractHalving, -1, -1, {INS_sve_shsub, INS_sve_uhsub, INS_sve_shsub, INS_sve_uhsub, INS_sve_shsub, INS_sve_uhsub, INS_sve_shsub, INS_sve_uhsub, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)
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HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
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HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics)
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HARDWARE_INTRINSIC(Sve2, ShiftArithmeticRounded, -1, -1, {INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)

‎src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs‎

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Original file line numberDiff line numberDiff line change
@@ -1006,6 +1006,170 @@ internal Arm64() { }
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/// </summary>
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public static Vector<ulong> BitwiseSelectRightInverted(Vector<ulong> select, Vector<ulong> left, Vector<ulong> right) { throw new PlatformNotSupportedException(); }
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// Halving add
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/// <summary>
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/// svuint8_t svhadd[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
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/// svuint8_t svhadd[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
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/// svuint8_t svhadd[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
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/// UHADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// UHADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// UHADD Ztied2.B, Pg/M, Ztied2.B, Zop1.B
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/// </summary>
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public static Vector<byte> FusedAddHalving(Vector<byte> left, Vector<byte> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint16_t svhadd[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
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/// svint16_t svhadd[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2)
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/// svint16_t svhadd[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2)
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/// SHADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// SHADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// SHADD Ztied2.H, Pg/M, Ztied2.H, Zop1.H
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/// </summary>
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public static Vector<short> FusedAddHalving(Vector<short> left, Vector<short> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint32_t svhadd[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2)
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/// svint32_t svhadd[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2)
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/// svint32_t svhadd[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2)
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/// SHADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// SHADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// SHADD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
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/// </summary>
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public static Vector<int> FusedAddHalving(Vector<int> left, Vector<int> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint64_t svhadd[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)
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/// svint64_t svhadd[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2)
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/// svint64_t svhadd[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2)
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/// SHADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// SHADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// SHADD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
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/// </summary>
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public static Vector<long> FusedAddHalving(Vector<long> left, Vector<long> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint8_t svhadd[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2)
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/// svint8_t svhadd[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2)
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/// svint8_t svhadd[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2)
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/// SHADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// SHADD Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// SHADD Ztied2.B, Pg/M, Ztied2.B, Zop1.B
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/// </summary>
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public static Vector<sbyte> FusedAddHalving(Vector<sbyte> left, Vector<sbyte> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svuint16_t svhadd[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
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/// svuint16_t svhadd[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
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/// svuint16_t svhadd[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
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/// UHADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// UHADD Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// UHADD Ztied2.H, Pg/M, Ztied2.H, Zop1.H
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/// </summary>
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public static Vector<ushort> FusedAddHalving(Vector<ushort> left, Vector<ushort> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svuint32_t svhadd[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
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/// svuint32_t svhadd[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
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/// svuint32_t svhadd[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
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/// UHADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// UHADD Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// UHADD Ztied2.S, Pg/M, Ztied2.S, Zop1.S
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/// </summary>
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public static Vector<uint> FusedAddHalving(Vector<uint> left, Vector<uint> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svuint64_t svhadd[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
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/// svuint64_t svhadd[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
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/// svuint64_t svhadd[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
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/// UHADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// UHADD Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// UHADD Ztied2.D, Pg/M, Ztied2.D, Zop1.D
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/// </summary>
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public static Vector<ulong> FusedAddHalving(Vector<ulong> left, Vector<ulong> right) { throw new PlatformNotSupportedException(); }
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// Halving subtract
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/// <summary>
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/// svuint8_t svhsub[_u8]_m(svbool_t pg, svuint8_t op1, svuint8_t op2)
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/// svuint8_t svhsub[_u8]_x(svbool_t pg, svuint8_t op1, svuint8_t op2)
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/// svuint8_t svhsub[_u8]_z(svbool_t pg, svuint8_t op1, svuint8_t op2)
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/// UHSUB Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// UHSUB Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// UHSUBR Ztied2.B, Pg/M, Ztied2.B, Zop1.B
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/// </summary>
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public static Vector<byte> FusedSubtractHalving(Vector<byte> left, Vector<byte> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint16_t svhsub[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
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/// svint16_t svhsub[_s16]_x(svbool_t pg, svint16_t op1, svint16_t op2)
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/// svint16_t svhsub[_s16]_z(svbool_t pg, svint16_t op1, svint16_t op2)
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/// SHSUB Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// SHSUB Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// SHSUBR Ztied2.H, Pg/M, Ztied2.H, Zop1.H
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/// </summary>
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public static Vector<short> FusedSubtractHalving(Vector<short> left, Vector<short> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint32_t svhsub[_s32]_m(svbool_t pg, svint32_t op1, svint32_t op2)
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/// svint32_t svhsub[_s32]_x(svbool_t pg, svint32_t op1, svint32_t op2)
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/// svint32_t svhsub[_s32]_z(svbool_t pg, svint32_t op1, svint32_t op2)
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/// SHSUB Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// SHSUB Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// SHSUBR Ztied2.S, Pg/M, Ztied2.S, Zop1.S
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/// </summary>
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public static Vector<int> FusedSubtractHalving(Vector<int> left, Vector<int> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint64_t svhsub[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)
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/// svint64_t svhsub[_s64]_x(svbool_t pg, svint64_t op1, svint64_t op2)
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/// svint64_t svhsub[_s64]_z(svbool_t pg, svint64_t op1, svint64_t op2)
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/// SHSUB Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// SHSUB Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// SHSUBR Ztied2.D, Pg/M, Ztied2.D, Zop1.D
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/// </summary>
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public static Vector<long> FusedSubtractHalving(Vector<long> left, Vector<long> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svint8_t svhsub[_s8]_m(svbool_t pg, svint8_t op1, svint8_t op2)
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/// svint8_t svhsub[_s8]_x(svbool_t pg, svint8_t op1, svint8_t op2)
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/// svint8_t svhsub[_s8]_z(svbool_t pg, svint8_t op1, svint8_t op2)
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/// SHSUB Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// SHSUB Ztied1.B, Pg/M, Ztied1.B, Zop2.B
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/// SHSUBR Ztied2.B, Pg/M, Ztied2.B, Zop1.B
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/// </summary>
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public static Vector<sbyte> FusedSubtractHalving(Vector<sbyte> left, Vector<sbyte> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svuint16_t svhsub[_u16]_m(svbool_t pg, svuint16_t op1, svuint16_t op2)
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/// svuint16_t svhsub[_u16]_x(svbool_t pg, svuint16_t op1, svuint16_t op2)
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/// svuint16_t svhsub[_u16]_z(svbool_t pg, svuint16_t op1, svuint16_t op2)
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/// UHSUB Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// UHSUB Ztied1.H, Pg/M, Ztied1.H, Zop2.H
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/// UHSUBR Ztied2.H, Pg/M, Ztied2.H, Zop1.H
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/// </summary>
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public static Vector<ushort> FusedSubtractHalving(Vector<ushort> left, Vector<ushort> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svuint32_t svhsub[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
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/// svuint32_t svhsub[_u32]_x(svbool_t pg, svuint32_t op1, svuint32_t op2)
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/// svuint32_t svhsub[_u32]_z(svbool_t pg, svuint32_t op1, svuint32_t op2)
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/// UHSUB Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// UHSUB Ztied1.S, Pg/M, Ztied1.S, Zop2.S
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/// UHSUBR Ztied2.S, Pg/M, Ztied2.S, Zop1.S
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/// </summary>
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public static Vector<uint> FusedSubtractHalving(Vector<uint> left, Vector<uint> right) { throw new PlatformNotSupportedException(); }
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/// <summary>
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/// svuint64_t svhsub[_u64]_m(svbool_t pg, svuint64_t op1, svuint64_t op2)
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/// svuint64_t svhsub[_u64]_x(svbool_t pg, svuint64_t op1, svuint64_t op2)
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/// svuint64_t svhsub[_u64]_z(svbool_t pg, svuint64_t op1, svuint64_t op2)
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/// UHSUB Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// UHSUB Ztied1.D, Pg/M, Ztied1.D, Zop2.D
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/// UHSUBR Ztied2.D, Pg/M, Ztied2.D, Zop1.D
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/// </summary>
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public static Vector<ulong> FusedSubtractHalving(Vector<ulong> left, Vector<ulong> right) { throw new PlatformNotSupportedException(); }
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/// Interleaving Xor
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/// <summary>

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