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Merging formats SVE_AB_3A and SVE_AD_3A into SVE_AA_3A (#101754)
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+60
-55
lines changed

4 files changed

+60
-55
lines changed

‎src/coreclr/jit/codegenarm64test.cpp‎

Lines changed: 12 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -4572,14 +4572,24 @@ void CodeGen::genArm64EmitterUnitTestsSve()
45724572
INS_OPTS_SCALABLE_S); // EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
45734573
theEmitter->emitIns_R_R_R(INS_sve_orr, EA_SCALABLE, REG_V29, REG_P7, REG_V31,
45744574
INS_OPTS_SCALABLE_D); // ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4575-
4576-
// IF_SVE_AB_3A
45774575
theEmitter->emitIns_R_R_R(INS_sve_add, EA_SCALABLE, REG_V5, REG_P6, REG_V7,
45784576
INS_OPTS_SCALABLE_B); // ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
45794577
theEmitter->emitIns_R_R_R(INS_sve_sub, EA_SCALABLE, REG_V15, REG_P7, REG_V29,
45804578
INS_OPTS_SCALABLE_H); // SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
45814579
theEmitter->emitIns_R_R_R(INS_sve_subr, EA_SCALABLE, REG_V2, REG_P0, REG_V13,
45824580
INS_OPTS_SCALABLE_S); // SUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4581+
theEmitter->emitIns_R_R_R(INS_sve_smax, EA_SCALABLE, REG_V24, REG_P0, REG_V2,
4582+
INS_OPTS_SCALABLE_B); // SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4583+
theEmitter->emitIns_R_R_R(INS_sve_smin, EA_SCALABLE, REG_V9, REG_P1, REG_V27,
4584+
INS_OPTS_SCALABLE_H); // SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4585+
theEmitter->emitIns_R_R_R(INS_sve_sabd, EA_SCALABLE, REG_V5, REG_P2, REG_V6,
4586+
INS_OPTS_SCALABLE_B); // SABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4587+
theEmitter->emitIns_R_R_R(INS_sve_uabd, EA_SCALABLE, REG_V23, REG_P3, REG_V9,
4588+
INS_OPTS_SCALABLE_S); // UABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4589+
theEmitter->emitIns_R_R_R(INS_sve_umax, EA_SCALABLE, REG_V15, REG_P4, REG_V2,
4590+
INS_OPTS_SCALABLE_S); // UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4591+
theEmitter->emitIns_R_R_R(INS_sve_umin, EA_SCALABLE, REG_V12, REG_P7, REG_V0,
4592+
INS_OPTS_SCALABLE_D); // UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
45834593

45844594
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
45854595
// IF_SVE_AB_3B
@@ -4599,20 +4609,6 @@ void CodeGen::genArm64EmitterUnitTestsSve()
45994609
theEmitter->emitIns_R_R_R(INS_sve_udivr, EA_SCALABLE, REG_V13, REG_P7, REG_V15,
46004610
INS_OPTS_SCALABLE_D); // UDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
46014611

4602-
// IF_SVE_AD_3A
4603-
theEmitter->emitIns_R_R_R(INS_sve_smax, EA_SCALABLE, REG_V24, REG_P0, REG_V2,
4604-
INS_OPTS_SCALABLE_B); // SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4605-
theEmitter->emitIns_R_R_R(INS_sve_smin, EA_SCALABLE, REG_V9, REG_P1, REG_V27,
4606-
INS_OPTS_SCALABLE_H); // SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4607-
theEmitter->emitIns_R_R_R(INS_sve_sabd, EA_SCALABLE, REG_V5, REG_P2, REG_V6,
4608-
INS_OPTS_SCALABLE_B); // SABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4609-
theEmitter->emitIns_R_R_R(INS_sve_uabd, EA_SCALABLE, REG_V23, REG_P3, REG_V9,
4610-
INS_OPTS_SCALABLE_S); // UABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4611-
theEmitter->emitIns_R_R_R(INS_sve_umax, EA_SCALABLE, REG_V15, REG_P4, REG_V2,
4612-
INS_OPTS_SCALABLE_S); // UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4613-
theEmitter->emitIns_R_R_R(INS_sve_umin, EA_SCALABLE, REG_V12, REG_P7, REG_V0,
4614-
INS_OPTS_SCALABLE_D); // UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
4615-
46164612
// IF_SVE_AE_3A
46174613
theEmitter->emitIns_R_R_R(INS_sve_mul, EA_SCALABLE, REG_V5, REG_P1, REG_V3,
46184614
INS_OPTS_SCALABLE_D); // MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

‎src/coreclr/jit/emitarm64sve.cpp‎

Lines changed: 33 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,7 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt)
347347
const static insFormat formatEncode4J[4] = {IF_SVE_BV_2A, IF_SVE_BV_2A_A, IF_SVE_CP_3A, IF_SVE_CQ_3A};
348348
const static insFormat formatEncode4K[4] = {IF_SVE_IF_4A, IF_SVE_IF_4A_A, IF_SVE_IM_3A, IF_SVE_IN_4A};
349349
const static insFormat formatEncode4L[4] = {IF_SVE_IZ_4A, IF_SVE_IZ_4A_A, IF_SVE_JB_4A, IF_SVE_JM_3A};
350-
const static insFormat formatEncode3A[3] = {IF_SVE_AB_3A, IF_SVE_AT_3A, IF_SVE_EC_1A};
350+
const static insFormat formatEncode3A[3] = {IF_SVE_AA_3A, IF_SVE_AT_3A, IF_SVE_EC_1A};
351351
const static insFormat formatEncode3B[3] = {IF_SVE_BH_3A, IF_SVE_BH_3B, IF_SVE_BH_3B_A};
352352
const static insFormat formatEncode3C[3] = {IF_SVE_BW_2A, IF_SVE_CB_2A, IF_SVE_EB_1A};
353353
const static insFormat formatEncode3D[3] = {IF_SVE_BR_3A, IF_SVE_BR_3B, IF_SVE_CI_3A};
@@ -371,7 +371,7 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt)
371371
const static insFormat formatEncode3V[3] = {IF_SVE_JA_4A, IF_SVE_JB_4A, IF_SVE_JM_3A};
372372
const static insFormat formatEncode2AA[2] = {IF_SVE_ID_2A, IF_SVE_IE_2A};
373373
const static insFormat formatEncode2AB[2] = {IF_SVE_JG_2A, IF_SVE_JH_2A};
374-
const static insFormat formatEncode2AC[2] = {IF_SVE_AD_3A, IF_SVE_ED_1A};
374+
const static insFormat formatEncode2AC[2] = {IF_SVE_AA_3A, IF_SVE_ED_1A};
375375
const static insFormat formatEncode2AD[2] = {IF_SVE_AB_3B, IF_SVE_AT_3B};
376376
const static insFormat formatEncode2AE[2] = {IF_SVE_CG_2A, IF_SVE_CJ_2A};
377377
const static insFormat formatEncode2AF[2] = {IF_SVE_AE_3A, IF_SVE_BD_3A};
@@ -387,7 +387,7 @@ emitter::code_t emitter::emitInsCodeSve(instruction ins, insFormat fmt)
387387
const static insFormat formatEncode2AP[2] = {IF_SVE_GY_3B, IF_SVE_HA_3A};
388388
const static insFormat formatEncode2AQ[2] = {IF_SVE_GO_3A, IF_SVE_HC_3A};
389389
const static insFormat formatEncode2AR[2] = {IF_SVE_AP_3A, IF_SVE_CZ_4A};
390-
const static insFormat formatEncode2AT[2] = {IF_SVE_AB_3A, IF_SVE_EC_1A};
390+
const static insFormat formatEncode2AT[2] = {IF_SVE_AA_3A, IF_SVE_EC_1A};
391391
const static insFormat formatEncode2AU[2] = {IF_SVE_AH_3A, IF_SVE_BI_2A};
392392
const static insFormat formatEncode2AV[2] = {IF_SVE_BM_1A, IF_SVE_BN_1A};
393393
const static insFormat formatEncode2AW[2] = {IF_SVE_BO_1A, IF_SVE_BP_1A};
@@ -2947,7 +2947,7 @@ void emitter::emitInsSve_R_R_R(instruction ins,
29472947
{
29482948
assert(isLowPredicateRegister(reg2));
29492949
assert(insScalableOptsNone(sopt));
2950-
fmt = IF_SVE_AB_3A;
2950+
fmt = IF_SVE_AA_3A;
29512951
}
29522952
break;
29532953

@@ -2994,7 +2994,7 @@ void emitter::emitInsSve_R_R_R(instruction ins,
29942994
assert(isVectorRegister(reg3));
29952995
assert(insOptsScalableStandard(opt));
29962996
assert(insScalableOptsNone(sopt));
2997-
fmt = IF_SVE_AD_3A;
2997+
fmt = IF_SVE_AA_3A;
29982998
break;
29992999

30003000
case INS_sve_mul:
@@ -8017,11 +8017,9 @@ void emitter::emitIns_PRFOP_R_R_I(instruction ins,
80178017
case IF_SVE_HP_3B:
80188018
case IF_SVE_AR_4A:
80198019
case IF_SVE_BV_2A_A:
8020-
case IF_SVE_AB_3A:
80218020
case IF_SVE_ET_3A:
80228021
case IF_SVE_HU_4A:
80238022
case IF_SVE_HL_3B:
8024-
case IF_SVE_AD_3A:
80258023
case IF_SVE_AB_3B:
80268024
case IF_SVE_AE_3A:
80278025
case IF_SVE_EU_3A:
@@ -9905,10 +9903,9 @@ BYTE* emitter::emitOutput_InstrSve(BYTE* dst, instrDesc* id)
99059903
switch (fmt)
99069904
{
99079905
// Scalable.
9908-
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated)
9909-
case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated)
9906+
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations + integer add/subtract
9907+
// vectors + SVE integer min/max/difference (predicated)
99109908
case IF_SVE_AC_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated)
9911-
case IF_SVE_AD_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated)
99129909
case IF_SVE_AE_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer multiply vectors (predicated)
99139910
case IF_SVE_AF_3A: // ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (predicated)
99149911
case IF_SVE_AG_3A: // ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (quadwords)
@@ -12556,9 +12553,8 @@ void emitter::emitInsSveSanityCheck(instrDesc* id)
1255612553
break;
1255712554

1255812555
// Scalable.
12559-
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated)
12560-
case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated)
12561-
case IF_SVE_AD_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated)
12556+
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations + integer add/subtract
12557+
// vectors + SVE integer min/max/difference (predicated)
1256212558
case IF_SVE_AE_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer multiply vectors (predicated)
1256312559
case IF_SVE_AN_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by vector (predicated)
1256412560
case IF_SVE_CM_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector
@@ -14484,10 +14480,9 @@ void emitter::emitDispInsSveHelp(instrDesc* id)
1448414480
bitMaskImm bmi;
1448514481

1448614482
// <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
14487-
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated)
14488-
case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated)
14483+
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations + integer add/subtract
14484+
// vectors + SVE integer min/max/difference (predicated)
1448914485
case IF_SVE_AC_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated)
14490-
case IF_SVE_AD_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated)
1449114486
case IF_SVE_AE_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer multiply vectors (predicated)
1449214487
case IF_SVE_AN_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by vector (predicated)
1449314488
case IF_SVE_EP_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 integer halving add/subtract (predicated)
@@ -16342,16 +16337,32 @@ void emitter::getInsSveExecutionCharacteristics(instrDesc* id, insExecutionChara
1634216337
switch (id->idInsFmt())
1634316338
{
1634416339
// Predicate logical
16345-
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated)
16346-
result.insLatency = PERFSCORE_LATENCY_1C;
16347-
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
16340+
case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations + integer add/subtract
16341+
// vectors + SVE integer min/max/difference (predicated)
16342+
switch (ins)
16343+
{
16344+
case INS_sve_add:
16345+
case INS_sve_sub:
16346+
case INS_sve_subr:
16347+
case INS_sve_sabd:
16348+
case INS_sve_smax:
16349+
case INS_sve_smin:
16350+
case INS_sve_uabd:
16351+
case INS_sve_umax:
16352+
case INS_sve_umin:
16353+
result.insLatency = PERFSCORE_LATENCY_2C;
16354+
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
16355+
break;
16356+
16357+
default:
16358+
result.insLatency = PERFSCORE_LATENCY_1C;
16359+
result.insThroughput = PERFSCORE_THROUGHPUT_1C;
16360+
break;
16361+
}
1634816362
break;
1634916363

1635016364
// Arithmetic, basic
16351-
case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated)
1635216365
case IF_SVE_EP_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 integer halving add/subtract (predicated)
16353-
// Max/min, basic and pairwise
16354-
case IF_SVE_AD_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated)
1635516366
result.insLatency = PERFSCORE_LATENCY_2C;
1635616367
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
1635716368
break;

‎src/coreclr/jit/emitfmtsarm64sve.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -138,10 +138,8 @@ IF_DEF(SVE_2BS, IS_NONE, NONE) // Instruction has 2 possible encoding types, ty
138138
*****************************************************************************/
139139

140140
IF_DEF(SVE_AA_3A, IS_NONE, NONE) // SVE_AA_3A ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated)
141-
IF_DEF(SVE_AB_3A, IS_NONE, NONE) // SVE_AB_3A ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated)
142141
IF_DEF(SVE_AB_3B, IS_NONE, NONE) // SVE_AB_3B ................ ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated)
143142
IF_DEF(SVE_AC_3A, IS_NONE, NONE) // SVE_AC_3A ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated)
144-
IF_DEF(SVE_AD_3A, IS_NONE, NONE) // SVE_AD_3A ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated)
145143
IF_DEF(SVE_AE_3A, IS_NONE, NONE) // SVE_AE_3A ........xx...... ...gggmmmmmddddd -- SVE integer multiply vectors (predicated)
146144
IF_DEF(SVE_AF_3A, IS_NONE, NONE) // SVE_AF_3A ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (predicated)
147145
IF_DEF(SVE_AG_3A, IS_NONE, NONE) // SVE_AG_3A ........xx...... ...gggnnnnnddddd -- SVE bitwise logical reduction (quadwords)

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