Don't set RM field when fcvt doesn't round (#98857)

CPUs and QEMU tend to ignore it but according to RISC-V ISA fcvt.d.s or fcvt.d.w[u] never round so it is an error. Besides, external disassemblers choke on it.

Author: tomeksowi

src/coreclr/jit/emitriscv64.cpp

@@ -625,15 +625,17 @@ void emitter::emitIns_R_R(
         assert(isGeneralRegisterOrR0(reg2));
         code |= (reg1 & 0x1f) << 7;
         code |= reg2 << 15;
-        code |= 0x7 << 12;
+        if (INS_fcvt_d_w != ins && INS_fcvt_d_wu != ins) // fcvt.d.w[u] always produces an exact result
+            code |= 0x7 << 12;                           // round according to frm status register
     }
     else if (INS_fcvt_s_d == ins || INS_fcvt_d_s == ins)
     {
         assert(isFloatReg(reg1));
         assert(isFloatReg(reg2));
         code |= (reg1 & 0x1f) << 7;
         code |= (reg2 & 0x1f) << 15;
-        code |= 0x7 << 12;
+        if (INS_fcvt_d_s != ins) // fcvt.d.s never rounds
+            code |= 0x7 << 12;   // round according to frm status register
     }
     else
     {