Rewrite resets

Signed-off-by: Alex Forencich <[email protected]>

Author: alexforencich

rtl/arbiter.v

@@ -141,16 +141,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    grant_reg <= grant_next;
+    grant_valid_reg <= grant_valid_next;
+    grant_encoded_reg <= grant_encoded_next;
+    mask_reg <= mask_next;
+
     if (rst) begin
         grant_reg <= 0;
         grant_valid_reg <= 0;
         grant_encoded_reg <= 0;
         mask_reg <= 0;
-    end else begin
-        grant_reg <= grant_next;
-        grant_valid_reg <= grant_valid_next;
-        grant_encoded_reg <= grant_encoded_next;
-        mask_reg <= mask_next;
     end
 end
 

rtl/axis_adapter.v

@@ -516,15 +516,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -551,6 +545,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_arb_mux.v

@@ -238,15 +238,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -273,6 +267,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_broadcast.v

@@ -153,15 +153,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        s_axis_tready_reg <= 1'b0;
-        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-    end else begin
-        s_axis_tready_reg <= s_axis_tready_early;
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    s_axis_tready_reg <= s_axis_tready_early;
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_input_to_output) begin
@@ -188,6 +182,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= s_axis_tdest;
         temp_m_axis_tuser_reg <= s_axis_tuser;
     end
+
+    if (rst) begin
+        s_axis_tready_reg <= 1'b0;
+        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+    end
 end
 
 endmodule

rtl/axis_cobs_decode.v

@@ -230,20 +230,21 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+
+    count_reg <= count_next;
+    suppress_zero_reg <= suppress_zero_next;
+
+    temp_tdata_reg <= temp_tdata_next;
+    temp_tvalid_reg <= temp_tvalid_next;
+
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         state_reg <= STATE_IDLE;
         temp_tvalid_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        temp_tvalid_reg <= temp_tvalid_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
-
-    temp_tdata_reg <= temp_tdata_next;
-
-    count_reg <= count_next;
-    suppress_zero_reg <= suppress_zero_next;
 end
 
 // output datapath logic
@@ -299,15 +300,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -325,6 +320,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_cobs_encode.v

@@ -411,17 +411,17 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        input_state_reg <= INPUT_STATE_IDLE;
-        output_state_reg <= OUTPUT_STATE_IDLE;
-    end else begin
-        input_state_reg <= input_state_next;
-        output_state_reg <= output_state_next;
-    end
+    input_state_reg <= input_state_next;
+    output_state_reg <= output_state_next;
 
     input_count_reg <= input_count_next;
     output_count_reg <= output_count_next;
     fail_frame_reg <= fail_frame_next;
+
+    if (rst) begin
+        input_state_reg <= INPUT_STATE_IDLE;
+        output_state_reg <= OUTPUT_STATE_IDLE;
+    end
 end
 
 // output datapath logic
@@ -477,15 +477,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -503,6 +497,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

rtl/axis_crosspoint.v

@@ -121,33 +121,31 @@ assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {M_COUNT*USER_WIDTH{1'b0
 integer i;
 
 always @(posedge clk) begin
-    if (rst) begin
-        s_axis_tvalid_reg <= {S_COUNT{1'b0}};
-        m_axis_tvalid_reg <= {S_COUNT{1'b0}};
-        select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
-    end else begin
-        s_axis_tvalid_reg <= s_axis_tvalid;
-        for (i = 0; i < M_COUNT; i = i + 1) begin
-            m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
-        end
-        select_reg <= select;
-    end
-
     s_axis_tdata_reg <= s_axis_tdata;
     s_axis_tkeep_reg <= s_axis_tkeep;
+    s_axis_tvalid_reg <= s_axis_tvalid;
     s_axis_tlast_reg <= s_axis_tlast;
     s_axis_tid_reg   <= s_axis_tid;
     s_axis_tdest_reg <= s_axis_tdest;
     s_axis_tuser_reg <= s_axis_tuser;
 
+    select_reg <= select;
+
     for (i = 0; i < M_COUNT; i = i + 1) begin
         m_axis_tdata_reg[i*DATA_WIDTH +: DATA_WIDTH] <= s_axis_tdata_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DATA_WIDTH +: DATA_WIDTH];
         m_axis_tkeep_reg[i*KEEP_WIDTH +: KEEP_WIDTH] <= s_axis_tkeep_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*KEEP_WIDTH +: KEEP_WIDTH];
+        m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
         m_axis_tlast_reg[i]                          <= s_axis_tlast_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
         m_axis_tid_reg[i*ID_WIDTH +: ID_WIDTH]       <= s_axis_tid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*ID_WIDTH +: ID_WIDTH];
         m_axis_tdest_reg[i*DEST_WIDTH +: DEST_WIDTH] <= s_axis_tdest_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DEST_WIDTH +: DEST_WIDTH];
         m_axis_tuser_reg[i*USER_WIDTH +: USER_WIDTH] <= s_axis_tuser_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*USER_WIDTH +: USER_WIDTH];
     end
+
+    if (rst) begin
+        s_axis_tvalid_reg <= {S_COUNT{1'b0}};
+        m_axis_tvalid_reg <= {S_COUNT{1'b0}};
+        select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
+    end
 end
 
 endmodule

rtl/axis_demux.v

@@ -184,16 +184,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    select_reg <= select_next;
+    drop_reg <= drop_next;
+    frame_reg <= frame_next;
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         select_reg <= 2'd0;
         drop_reg <= 1'b0;
         frame_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        select_reg <= select_next;
-        drop_reg <= drop_next;
-        frame_reg <= frame_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
 end
 
@@ -259,15 +259,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -294,6 +288,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+    end
 end
 
 endmodule