diff --git a/ports/espressif/boards/unexpectedmaker_edges3d/board.c b/ports/espressif/boards/unexpectedmaker_edges3d/board.c
new file mode 100644
index 0000000000000..a3a9eec047145
--- /dev/null
+++ b/ports/espressif/boards/unexpectedmaker_edges3d/board.c
@@ -0,0 +1,9 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2020 Scott Shawcroft for Adafruit Industries
+//
+// SPDX-License-Identifier: MIT
+
+#include "supervisor/board.h"
+
+// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here.
diff --git a/ports/espressif/boards/unexpectedmaker_edges3d/mpconfigboard.h b/ports/espressif/boards/unexpectedmaker_edges3d/mpconfigboard.h
new file mode 100644
index 0000000000000..27be4ffd1ceb7
--- /dev/null
+++ b/ports/espressif/boards/unexpectedmaker_edges3d/mpconfigboard.h
@@ -0,0 +1,23 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2019 Scott Shawcroft for Adafruit
+// Industries
+//
+// SPDX-License-Identifier: MIT
+
+#pragma once
+
+// Micropython setup
+
+#define MICROPY_HW_BOARD_NAME "EDGES3D"
+#define MICROPY_HW_MCU_NAME "ESP32S3"
+
+#define DEFAULT_I2C_BUS_SCL (&pin_GPIO9)
+#define DEFAULT_I2C_BUS_SDA (&pin_GPIO8)
+
+#define DEFAULT_SPI_BUS_SCK (&pin_GPIO4)
+#define DEFAULT_SPI_BUS_MOSI (&pin_GPIO7)
+#define DEFAULT_SPI_BUS_MISO (&pin_GPIO5)
+
+#define DEFAULT_UART_BUS_RX (&pin_GPIO44)
+#define DEFAULT_UART_BUS_TX (&pin_GPIO43)
diff --git a/ports/espressif/boards/unexpectedmaker_edges3d/mpconfigboard.mk b/ports/espressif/boards/unexpectedmaker_edges3d/mpconfigboard.mk
new file mode 100644
index 0000000000000..01e2edc4164ac
--- /dev/null
+++ b/ports/espressif/boards/unexpectedmaker_edges3d/mpconfigboard.mk
@@ -0,0 +1,16 @@
+USB_VID = 0x303A
+USB_PID = 0x82DD
+USB_PRODUCT = "EDGES3D"
+USB_MANUFACTURER = "UnexpectedMaker"
+
+IDF_TARGET = esp32s3
+
+CIRCUITPY_ESP_FLASH_SIZE = 8MB
+CIRCUITPY_ESP_FLASH_MODE = qio
+CIRCUITPY_ESP_FLASH_FREQ = 80m
+
+CIRCUITPY_ESP_PSRAM_SIZE = 2MB
+CIRCUITPY_ESP_PSRAM_MODE = qio
+CIRCUITPY_ESP_PSRAM_FREQ = 80m
+
+CIRCUITPY_STAGE = 1
diff --git a/ports/espressif/boards/unexpectedmaker_edges3d/pins.c b/ports/espressif/boards/unexpectedmaker_edges3d/pins.c
new file mode 100644
index 0000000000000..b753ea207b179
--- /dev/null
+++ b/ports/espressif/boards/unexpectedmaker_edges3d/pins.c
@@ -0,0 +1,126 @@
+// This file is part of the CircuitPython project: https://circuitpython.org
+//
+// SPDX-FileCopyrightText: Copyright (c) 2020 Scott Shawcroft for Adafruit
+// Industries
+//
+// SPDX-License-Identifier: MIT
+
+#include "shared-bindings/board/__init__.h"
+
+static const mp_rom_map_elem_t board_module_globals_table[] = {
+    CIRCUITPYTHON_BOARD_DICT_STANDARD_ITEMS
+
+    {MP_ROM_QSTR(MP_QSTR_IO0), MP_ROM_PTR(&pin_GPIO0)},
+    {MP_ROM_QSTR(MP_QSTR_D0), MP_ROM_PTR(&pin_GPIO0)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO1), MP_ROM_PTR(&pin_GPIO1)},
+    {MP_ROM_QSTR(MP_QSTR_A0), MP_ROM_PTR(&pin_GPIO1)},
+    {MP_ROM_QSTR(MP_QSTR_D1), MP_ROM_PTR(&pin_GPIO1)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO2), MP_ROM_PTR(&pin_GPIO2)},
+    {MP_ROM_QSTR(MP_QSTR_A1), MP_ROM_PTR(&pin_GPIO2)},
+    {MP_ROM_QSTR(MP_QSTR_D2), MP_ROM_PTR(&pin_GPIO2)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO3), MP_ROM_PTR(&pin_GPIO3)},
+    {MP_ROM_QSTR(MP_QSTR_A2), MP_ROM_PTR(&pin_GPIO3)},
+    {MP_ROM_QSTR(MP_QSTR_D3), MP_ROM_PTR(&pin_GPIO3)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO4), MP_ROM_PTR(&pin_GPIO4)},
+    {MP_ROM_QSTR(MP_QSTR_A3), MP_ROM_PTR(&pin_GPIO4)},
+    {MP_ROM_QSTR(MP_QSTR_D4), MP_ROM_PTR(&pin_GPIO4)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO5), MP_ROM_PTR(&pin_GPIO5)},
+    {MP_ROM_QSTR(MP_QSTR_A4), MP_ROM_PTR(&pin_GPIO5)},
+    {MP_ROM_QSTR(MP_QSTR_D5), MP_ROM_PTR(&pin_GPIO5)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO6), MP_ROM_PTR(&pin_GPIO6)},
+    {MP_ROM_QSTR(MP_QSTR_FG_INT), MP_ROM_PTR(&pin_GPIO6)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO7), MP_ROM_PTR(&pin_GPIO7)},
+    {MP_ROM_QSTR(MP_QSTR_A6), MP_ROM_PTR(&pin_GPIO7)},
+    {MP_ROM_QSTR(MP_QSTR_D7), MP_ROM_PTR(&pin_GPIO7)},
+
+    {MP_ROM_QSTR(MP_QSTR_SDA), MP_ROM_PTR(&pin_GPIO8)},
+    {MP_ROM_QSTR(MP_QSTR_IO8), MP_ROM_PTR(&pin_GPIO8)},
+    {MP_ROM_QSTR(MP_QSTR_A7), MP_ROM_PTR(&pin_GPIO8)},
+    {MP_ROM_QSTR(MP_QSTR_D8), MP_ROM_PTR(&pin_GPIO8)},
+
+    {MP_ROM_QSTR(MP_QSTR_SCL), MP_ROM_PTR(&pin_GPIO9)},
+    {MP_ROM_QSTR(MP_QSTR_IO9), MP_ROM_PTR(&pin_GPIO9)},
+    {MP_ROM_QSTR(MP_QSTR_A8), MP_ROM_PTR(&pin_GPIO9)},
+    {MP_ROM_QSTR(MP_QSTR_D9), MP_ROM_PTR(&pin_GPIO9)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO10), MP_ROM_PTR(&pin_GPIO10)},
+    {MP_ROM_QSTR(MP_QSTR_A9), MP_ROM_PTR(&pin_GPIO10)},
+    {MP_ROM_QSTR(MP_QSTR_D10), MP_ROM_PTR(&pin_GPIO10)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO11), MP_ROM_PTR(&pin_GPIO11)},
+    {MP_ROM_QSTR(MP_QSTR_A10), MP_ROM_PTR(&pin_GPIO11)},
+    {MP_ROM_QSTR(MP_QSTR_D11), MP_ROM_PTR(&pin_GPIO11)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO12), MP_ROM_PTR(&pin_GPIO12)},
+    {MP_ROM_QSTR(MP_QSTR_A11), MP_ROM_PTR(&pin_GPIO12)},
+    {MP_ROM_QSTR(MP_QSTR_D12), MP_ROM_PTR(&pin_GPIO12)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO13), MP_ROM_PTR(&pin_GPIO13)},
+    {MP_ROM_QSTR(MP_QSTR_A12), MP_ROM_PTR(&pin_GPIO13)},
+    {MP_ROM_QSTR(MP_QSTR_D13), MP_ROM_PTR(&pin_GPIO13)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO14), MP_ROM_PTR(&pin_GPIO14)},
+    {MP_ROM_QSTR(MP_QSTR_A13), MP_ROM_PTR(&pin_GPIO14)},
+    {MP_ROM_QSTR(MP_QSTR_D14), MP_ROM_PTR(&pin_GPIO14)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO15), MP_ROM_PTR(&pin_GPIO15)},
+    {MP_ROM_QSTR(MP_QSTR_A14), MP_ROM_PTR(&pin_GPIO15)},
+    {MP_ROM_QSTR(MP_QSTR_D15), MP_ROM_PTR(&pin_GPIO15)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO16), MP_ROM_PTR(&pin_GPIO16)},
+    {MP_ROM_QSTR(MP_QSTR_A15), MP_ROM_PTR(&pin_GPIO16)},
+    {MP_ROM_QSTR(MP_QSTR_D16), MP_ROM_PTR(&pin_GPIO16)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO17), MP_ROM_PTR(&pin_GPIO17)},
+    {MP_ROM_QSTR(MP_QSTR_A16), MP_ROM_PTR(&pin_GPIO17)},
+    {MP_ROM_QSTR(MP_QSTR_D17), MP_ROM_PTR(&pin_GPIO17)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO18), MP_ROM_PTR(&pin_GPIO18)},
+    {MP_ROM_QSTR(MP_QSTR_A17), MP_ROM_PTR(&pin_GPIO18)},
+    {MP_ROM_QSTR(MP_QSTR_D18), MP_ROM_PTR(&pin_GPIO18)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO21), MP_ROM_PTR(&pin_GPIO21)},
+    {MP_ROM_QSTR(MP_QSTR_D21), MP_ROM_PTR(&pin_GPIO21)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO39), MP_ROM_PTR(&pin_GPIO39)},
+    {MP_ROM_QSTR(MP_QSTR_D39), MP_ROM_PTR(&pin_GPIO39)},
+    {MP_ROM_QSTR(MP_QSTR_MTCK), MP_ROM_PTR(&pin_GPIO39)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO40), MP_ROM_PTR(&pin_GPIO40)},
+    {MP_ROM_QSTR(MP_QSTR_D40), MP_ROM_PTR(&pin_GPIO40)},
+    {MP_ROM_QSTR(MP_QSTR_MTDO), MP_ROM_PTR(&pin_GPIO40)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO41), MP_ROM_PTR(&pin_GPIO41)},
+    {MP_ROM_QSTR(MP_QSTR_D41), MP_ROM_PTR(&pin_GPIO41)},
+    {MP_ROM_QSTR(MP_QSTR_MTDI), MP_ROM_PTR(&pin_GPIO41)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO42), MP_ROM_PTR(&pin_GPIO42)},
+    {MP_ROM_QSTR(MP_QSTR_D42), MP_ROM_PTR(&pin_GPIO42)},
+    {MP_ROM_QSTR(MP_QSTR_MTMS), MP_ROM_PTR(&pin_GPIO42)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO43), MP_ROM_PTR(&pin_GPIO43)},
+    {MP_ROM_QSTR(MP_QSTR_D43), MP_ROM_PTR(&pin_GPIO43)},
+    {MP_ROM_QSTR(MP_QSTR_TX), MP_ROM_PTR(&pin_GPIO43)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO44), MP_ROM_PTR(&pin_GPIO44)},
+    {MP_ROM_QSTR(MP_QSTR_D44), MP_ROM_PTR(&pin_GPIO44)},
+    {MP_ROM_QSTR(MP_QSTR_RX), MP_ROM_PTR(&pin_GPIO44)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO45), MP_ROM_PTR(&pin_GPIO45)},
+    {MP_ROM_QSTR(MP_QSTR_D45), MP_ROM_PTR(&pin_GPIO45)},
+
+    {MP_ROM_QSTR(MP_QSTR_IO46), MP_ROM_PTR(&pin_GPIO46)},
+    {MP_ROM_QSTR(MP_QSTR_D46), MP_ROM_PTR(&pin_GPIO46)},
+
+    {MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&board_i2c_obj)},
+    {MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&board_spi_obj)},
+    {MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&board_uart_obj)},
+};
+MP_DEFINE_CONST_DICT(board_module_globals, board_module_globals_table);
diff --git a/ports/espressif/boards/unexpectedmaker_edges3d/sdkconfig b/ports/espressif/boards/unexpectedmaker_edges3d/sdkconfig
new file mode 100644
index 0000000000000..e962866216039
--- /dev/null
+++ b/ports/espressif/boards/unexpectedmaker_edges3d/sdkconfig
@@ -0,0 +1,14 @@
+#
+# Espressif IoT Development Framework Configuration
+#
+#
+# Component config
+#
+#
+# LWIP
+#
+# end of LWIP
+
+# end of Component config
+
+# end of Espressif IoT Development Framework Configuration