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pmachatadavem330
pmachata
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davem330
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mlxsw: spectrum_buffers: Add Spectrum-2 shared buffer configuration
Customize the tables related to shared buffer configuration to match the current recommendation for Spectrum-2 systems. Signed-off-by: Petr Machata <[email protected]> Signed-off-by: Ido Schimmel <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/mellanox/mlxsw/spectrum_buffers.c‎

Lines changed: 106 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ struct mlxsw_sp_sb_pool_des {
4949
};
5050

5151
/* Order ingress pools before egress pools. */
52-
static const struct mlxsw_sp_sb_pool_des mlxsw_sp_sb_pool_dess[] = {
52+
static const struct mlxsw_sp_sb_pool_des mlxsw_sp1_sb_pool_dess[] = {
5353
{MLXSW_REG_SBXX_DIR_INGRESS, 0},
5454
{MLXSW_REG_SBXX_DIR_INGRESS, 1},
5555
{MLXSW_REG_SBXX_DIR_INGRESS, 2},
@@ -61,6 +61,17 @@ static const struct mlxsw_sp_sb_pool_des mlxsw_sp_sb_pool_dess[] = {
6161
{MLXSW_REG_SBXX_DIR_EGRESS, 15},
6262
};
6363

64+
static const struct mlxsw_sp_sb_pool_des mlxsw_sp2_sb_pool_dess[] = {
65+
{MLXSW_REG_SBXX_DIR_INGRESS, 0},
66+
{MLXSW_REG_SBXX_DIR_INGRESS, 1},
67+
{MLXSW_REG_SBXX_DIR_INGRESS, 2},
68+
{MLXSW_REG_SBXX_DIR_INGRESS, 3},
69+
{MLXSW_REG_SBXX_DIR_EGRESS, 0},
70+
{MLXSW_REG_SBXX_DIR_EGRESS, 1},
71+
{MLXSW_REG_SBXX_DIR_EGRESS, 2},
72+
{MLXSW_REG_SBXX_DIR_EGRESS, 3},
73+
};
74+
6475
#define MLXSW_SP_SB_ING_TC_COUNT 8
6576
#define MLXSW_SP_SB_EG_TC_COUNT 16
6677

@@ -366,32 +377,53 @@ static void mlxsw_sp_sb_ports_fini(struct mlxsw_sp *mlxsw_sp)
366377
kfree(mlxsw_sp->sb->ports);
367378
}
368379

369-
#define MLXSW_SP_SB_PR_INGRESS_SIZE 12440000
370-
#define MLXSW_SP_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
371-
#define MLXSW_SP_SB_PR_EGRESS_SIZE 13232000
372-
373380
#define MLXSW_SP_SB_PR(_mode, _size) \
374381
{ \
375382
.mode = _mode, \
376383
.size = _size, \
377384
}
378385

379-
static const struct mlxsw_sp_sb_pr mlxsw_sp_sb_prs[] = {
386+
#define MLXSW_SP1_SB_PR_INGRESS_SIZE 12440000
387+
#define MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
388+
#define MLXSW_SP1_SB_PR_EGRESS_SIZE 13232000
389+
390+
static const struct mlxsw_sp_sb_pr mlxsw_sp1_sb_prs[] = {
380391
/* Ingress pools. */
381392
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
382-
MLXSW_SP_SB_PR_INGRESS_SIZE),
393+
MLXSW_SP1_SB_PR_INGRESS_SIZE),
383394
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
384395
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
385396
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
386-
MLXSW_SP_SB_PR_INGRESS_MNG_SIZE),
397+
MLXSW_SP1_SB_PR_INGRESS_MNG_SIZE),
387398
/* Egress pools. */
388-
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, MLXSW_SP_SB_PR_EGRESS_SIZE),
399+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
400+
MLXSW_SP1_SB_PR_EGRESS_SIZE),
389401
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
390402
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
391403
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC, 0),
392404
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, MLXSW_SP_SB_INFI),
393405
};
394406

407+
#define MLXSW_SP2_SB_PR_INGRESS_SIZE 40960000
408+
#define MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE (200 * 1000)
409+
#define MLXSW_SP2_SB_PR_EGRESS_SIZE 40960000
410+
411+
static const struct mlxsw_sp_sb_pr mlxsw_sp2_sb_prs[] = {
412+
/* Ingress pools. */
413+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
414+
MLXSW_SP2_SB_PR_INGRESS_SIZE),
415+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
416+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
417+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
418+
MLXSW_SP2_SB_PR_INGRESS_MNG_SIZE),
419+
/* Egress pools. */
420+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_DYNAMIC,
421+
MLXSW_SP2_SB_PR_EGRESS_SIZE),
422+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
423+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
424+
MLXSW_SP_SB_PR(MLXSW_REG_SBPR_MODE_STATIC, 0),
425+
};
426+
395427
static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
396428
const struct mlxsw_sp_sb_pr *prs,
397429
size_t prs_len)
@@ -424,7 +456,7 @@ static int mlxsw_sp_sb_prs_init(struct mlxsw_sp *mlxsw_sp,
424456
.pool_index = _pool, \
425457
}
426458

427-
static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
459+
static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_ingress[] = {
428460
MLXSW_SP_SB_CM(10000, 8, 0),
429461
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
430462
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
@@ -437,7 +469,20 @@ static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_ingress[] = {
437469
MLXSW_SP_SB_CM(20000, 1, 3),
438470
};
439471

440-
static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
472+
static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_ingress[] = {
473+
MLXSW_SP_SB_CM(0, 7, 0),
474+
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
475+
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
476+
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
477+
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
478+
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
479+
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
480+
MLXSW_SP_SB_CM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN, 0),
481+
MLXSW_SP_SB_CM(0, 0, 0), /* dummy, this PG does not exist */
482+
MLXSW_SP_SB_CM(20000, 1, 3),
483+
};
484+
485+
static const struct mlxsw_sp_sb_cm mlxsw_sp1_sb_cms_egress[] = {
441486
MLXSW_SP_SB_CM(1500, 9, 4),
442487
MLXSW_SP_SB_CM(1500, 9, 4),
443488
MLXSW_SP_SB_CM(1500, 9, 4),
@@ -457,6 +502,26 @@ static const struct mlxsw_sp_sb_cm mlxsw_sp_sb_cms_egress[] = {
457502
MLXSW_SP_SB_CM(1, 0xff, 4),
458503
};
459504

505+
static const struct mlxsw_sp_sb_cm mlxsw_sp2_sb_cms_egress[] = {
506+
MLXSW_SP_SB_CM(0, 7, 4),
507+
MLXSW_SP_SB_CM(0, 7, 4),
508+
MLXSW_SP_SB_CM(0, 7, 4),
509+
MLXSW_SP_SB_CM(0, 7, 4),
510+
MLXSW_SP_SB_CM(0, 7, 4),
511+
MLXSW_SP_SB_CM(0, 7, 4),
512+
MLXSW_SP_SB_CM(0, 7, 4),
513+
MLXSW_SP_SB_CM(0, 7, 4),
514+
MLXSW_SP_SB_CM(0, 7, 4),
515+
MLXSW_SP_SB_CM(0, 7, 4),
516+
MLXSW_SP_SB_CM(0, 7, 4),
517+
MLXSW_SP_SB_CM(0, 7, 4),
518+
MLXSW_SP_SB_CM(0, 7, 4),
519+
MLXSW_SP_SB_CM(0, 7, 4),
520+
MLXSW_SP_SB_CM(0, 7, 4),
521+
MLXSW_SP_SB_CM(0, 7, 4),
522+
MLXSW_SP_SB_CM(1, 0xff, 4),
523+
};
524+
460525
#define MLXSW_SP_CPU_PORT_SB_CM MLXSW_SP_SB_CM(0, 0, 4)
461526

462527
static const struct mlxsw_sp_sb_cm mlxsw_sp_cpu_port_sb_cms[] = {
@@ -575,7 +640,7 @@ static int mlxsw_sp_cpu_port_sb_cms_init(struct mlxsw_sp *mlxsw_sp)
575640
.max_buff = _max_buff, \
576641
}
577642

578-
static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
643+
static const struct mlxsw_sp_sb_pm mlxsw_sp1_sb_pms[] = {
579644
/* Ingress pools. */
580645
MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
581646
MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN),
@@ -589,6 +654,19 @@ static const struct mlxsw_sp_sb_pm mlxsw_sp_sb_pms[] = {
589654
MLXSW_SP_SB_PM(10000, 90000),
590655
};
591656

657+
static const struct mlxsw_sp_sb_pm mlxsw_sp2_sb_pms[] = {
658+
/* Ingress pools. */
659+
MLXSW_SP_SB_PM(0, 7),
660+
MLXSW_SP_SB_PM(0, 0),
661+
MLXSW_SP_SB_PM(0, 0),
662+
MLXSW_SP_SB_PM(0, MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX),
663+
/* Egress pools. */
664+
MLXSW_SP_SB_PM(0, 7),
665+
MLXSW_SP_SB_PM(0, 0),
666+
MLXSW_SP_SB_PM(0, 0),
667+
MLXSW_SP_SB_PM(0, 0),
668+
};
669+
592670
static int mlxsw_sp_port_sb_pms_init(struct mlxsw_sp_port *mlxsw_sp_port)
593671
{
594672
struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
@@ -680,32 +758,32 @@ static void mlxsw_sp_pool_count(struct mlxsw_sp *mlxsw_sp,
680758
}
681759

682760
const struct mlxsw_sp_sb_vals mlxsw_sp1_sb_vals = {
683-
.pool_count = ARRAY_SIZE(mlxsw_sp_sb_pool_dess),
684-
.pool_dess = mlxsw_sp_sb_pool_dess,
685-
.pms = mlxsw_sp_sb_pms,
686-
.prs = mlxsw_sp_sb_prs,
761+
.pool_count = ARRAY_SIZE(mlxsw_sp1_sb_pool_dess),
762+
.pool_dess = mlxsw_sp1_sb_pool_dess,
763+
.pms = mlxsw_sp1_sb_pms,
764+
.prs = mlxsw_sp1_sb_prs,
687765
.mms = mlxsw_sp_sb_mms,
688-
.cms_ingress = mlxsw_sp_sb_cms_ingress,
689-
.cms_egress = mlxsw_sp_sb_cms_egress,
766+
.cms_ingress = mlxsw_sp1_sb_cms_ingress,
767+
.cms_egress = mlxsw_sp1_sb_cms_egress,
690768
.cms_cpu = mlxsw_sp_cpu_port_sb_cms,
691769
.mms_count = ARRAY_SIZE(mlxsw_sp_sb_mms),
692-
.cms_ingress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_ingress),
693-
.cms_egress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_egress),
770+
.cms_ingress_count = ARRAY_SIZE(mlxsw_sp1_sb_cms_ingress),
771+
.cms_egress_count = ARRAY_SIZE(mlxsw_sp1_sb_cms_egress),
694772
.cms_cpu_count = ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms),
695773
};
696774

697775
const struct mlxsw_sp_sb_vals mlxsw_sp2_sb_vals = {
698-
.pool_count = ARRAY_SIZE(mlxsw_sp_sb_pool_dess),
699-
.pool_dess = mlxsw_sp_sb_pool_dess,
700-
.pms = mlxsw_sp_sb_pms,
701-
.prs = mlxsw_sp_sb_prs,
776+
.pool_count = ARRAY_SIZE(mlxsw_sp2_sb_pool_dess),
777+
.pool_dess = mlxsw_sp2_sb_pool_dess,
778+
.pms = mlxsw_sp2_sb_pms,
779+
.prs = mlxsw_sp2_sb_prs,
702780
.mms = mlxsw_sp_sb_mms,
703-
.cms_ingress = mlxsw_sp_sb_cms_ingress,
704-
.cms_egress = mlxsw_sp_sb_cms_egress,
781+
.cms_ingress = mlxsw_sp2_sb_cms_ingress,
782+
.cms_egress = mlxsw_sp2_sb_cms_egress,
705783
.cms_cpu = mlxsw_sp_cpu_port_sb_cms,
706784
.mms_count = ARRAY_SIZE(mlxsw_sp_sb_mms),
707-
.cms_ingress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_ingress),
708-
.cms_egress_count = ARRAY_SIZE(mlxsw_sp_sb_cms_egress),
785+
.cms_ingress_count = ARRAY_SIZE(mlxsw_sp2_sb_cms_ingress),
786+
.cms_egress_count = ARRAY_SIZE(mlxsw_sp2_sb_cms_egress),
709787
.cms_cpu_count = ARRAY_SIZE(mlxsw_sp_cpu_port_sb_cms),
710788
};
711789

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