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Merged main:6f618a7b8249e7baa3b2d18f8bbec3c5b6f6d24e into amd-gfx:e5edfda5900b
Local branch amd-gfx e5edfda Merged main:65b7cbbd8735b90933369364153b982d498f649a into amd-gfx:2f9a9b483f9f Remote branch main 6f618a7 Update my email
2 parents e5edfda + 6f618a7 commit 08f1863

18 files changed

+636
-259
lines changed

‎.mailmap‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@
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<[email protected]> <[email protected]>
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<[email protected]> <[email protected]>
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<[email protected]> <[email protected]>
33-
<[email protected]> <[email protected]>
33+
<[email protected]> <[email protected]> <[email protected]>
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<[email protected]> <[email protected]>
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<[email protected]> <[email protected]>
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Jianjian GUAN <[email protected]>

‎libcxx/test/support/atomic_helpers.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,15 +30,15 @@
3030
# define TEST_ATOMIC_LONG_LOCK_FREE __GCC_ATOMIC_LONG_LOCK_FREE
3131
# define TEST_ATOMIC_LLONG_LOCK_FREE __GCC_ATOMIC_LLONG_LOCK_FREE
3232
# define TEST_ATOMIC_POINTER_LOCK_FREE __GCC_ATOMIC_POINTER_LOCK_FREE
33-
#elif TEST_COMPILER_MSVC
33+
#elif defined(TEST_COMPILER_MSVC)
3434
// This is lifted from STL/stl/inc/atomic on github for the purposes of
3535
// keeping the tests compiling for MSVC's STL. It's not a perfect solution
3636
// but at least the tests will keep running.
3737
//
3838
// Note MSVC's STL never produces a type that is sometimes lock free, but not always lock free.
3939
template <class T, size_t Size = sizeof(T)>
40-
constexpr bool msvc_is_lock_free_macro_value() {
41-
return (Size <= 8 && (Size & Size - 1) == 0) ? 2 : 0;
40+
constexpr int msvc_is_lock_free_macro_value() {
41+
return (Size <= 8 && (Size & (Size - 1)) == 0) ? 2 : 0;
4242
}
4343
# define TEST_ATOMIC_CHAR_LOCK_FREE ::msvc_is_lock_free_macro_value<char>()
4444
# define TEST_ATOMIC_SHORT_LOCK_FREE ::msvc_is_lock_free_macro_value<short>()

‎llvm/CREDITS.TXT‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -432,10 +432,6 @@ W: http://vladimir_prus.blogspot.com
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E: [email protected]
433433
D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
434434

435-
N: QIU Chaofan
436-
E: [email protected]
437-
D: PowerPC Backend Developer
438-
439435
N: Kalle Raiskila
440436
E: [email protected]
441437
D: Some bugfixes to CellSPU

‎llvm/include/llvm/Config/llvm-config.h.cmake‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 509536
19+
#define LLVM_MAIN_REVISION 509543
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/include/llvm/IR/VPIntrinsics.def‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -722,27 +722,29 @@ HELPER_REGISTER_REDUCTION_VP(vp_reduce_fminimum, VP_REDUCE_FMINIMUM,
722722
#error \
723723
"The internal helper macro HELPER_REGISTER_REDUCTION_SEQ_VP is already defined!"
724724
#endif
725-
#define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, INTRIN) \
725+
#define HELPER_REGISTER_REDUCTION_SEQ_VP(VPID, VPSD, SEQ_VPSD, SDOPC, SEQ_SDOPC, INTRIN) \
726726
BEGIN_REGISTER_VP_INTRINSIC(VPID, 2, 3) \
727727
BEGIN_REGISTER_VP_SDNODE(VPSD, 1, VPID, 2, 3) \
728728
VP_PROPERTY_REDUCTION(0, 1) \
729+
VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) \
729730
END_REGISTER_VP_SDNODE(VPSD) \
730731
BEGIN_REGISTER_VP_SDNODE(SEQ_VPSD, 1, VPID, 2, 3) \
731732
HELPER_MAP_VPID_TO_VPSD(VPID, SEQ_VPSD) \
733+
VP_PROPERTY_FUNCTIONAL_SDOPC(SEQ_SDOPC) \
732734
VP_PROPERTY_REDUCTION(0, 1) \
733735
END_REGISTER_VP_SDNODE(SEQ_VPSD) \
734736
VP_PROPERTY_FUNCTIONAL_INTRINSIC(INTRIN) \
735737
END_REGISTER_VP_INTRINSIC(VPID)
736738

737739
// llvm.vp.reduce.fadd(start,x,mask,vlen)
738740
HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fadd, VP_REDUCE_FADD,
739-
VP_REDUCE_SEQ_FADD,
740-
vector_reduce_fadd)
741+
VP_REDUCE_SEQ_FADD, VECREDUCE_FADD,
742+
VECREDUCE_SEQ_FADD, vector_reduce_fadd)
741743

742744
// llvm.vp.reduce.fmul(start,x,mask,vlen)
743745
HELPER_REGISTER_REDUCTION_SEQ_VP(vp_reduce_fmul, VP_REDUCE_FMUL,
744-
VP_REDUCE_SEQ_FMUL,
745-
vector_reduce_fmul)
746+
VP_REDUCE_SEQ_FMUL, VECREDUCE_FMUL,
747+
VECREDUCE_SEQ_FMUL, vector_reduce_fmul)
746748

747749
#undef HELPER_REGISTER_REDUCTION_SEQ_VP
748750

‎llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp‎

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7311,8 +7311,6 @@ SDValue DAGTypeLegalizer::WidenVecOp_VECREDUCE(SDNode *N) {
73117311
// Generate a vp.reduce_op if it is custom/legal for the target. This avoids
73127312
// needing to pad the source vector, because the inactive lanes can simply be
73137313
// disabled and not contribute to the result.
7314-
// TODO: VECREDUCE_FADD, VECREDUCE_FMUL aren't currently mapped correctly,
7315-
// and thus don't take this path.
73167314
if (auto VPOpcode = ISD::getVPForBaseOpcode(Opc);
73177315
VPOpcode && TLI.isOperationLegalOrCustom(*VPOpcode, WideVT)) {
73187316
SDValue Start = NeutralElem;
@@ -7351,6 +7349,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_VECREDUCE_SEQ(SDNode *N) {
73517349
SDValue VecOp = N->getOperand(1);
73527350
SDValue Op = GetWidenedVector(VecOp);
73537351

7352+
EVT VT = N->getValueType(0);
73547353
EVT OrigVT = VecOp.getValueType();
73557354
EVT WideVT = Op.getValueType();
73567355
EVT ElemVT = OrigVT.getVectorElementType();
@@ -7364,6 +7363,19 @@ SDValue DAGTypeLegalizer::WidenVecOp_VECREDUCE_SEQ(SDNode *N) {
73647363
unsigned OrigElts = OrigVT.getVectorMinNumElements();
73657364
unsigned WideElts = WideVT.getVectorMinNumElements();
73667365

7366+
// Generate a vp.reduce_op if it is custom/legal for the target. This avoids
7367+
// needing to pad the source vector, because the inactive lanes can simply be
7368+
// disabled and not contribute to the result.
7369+
if (auto VPOpcode = ISD::getVPForBaseOpcode(Opc);
7370+
VPOpcode && TLI.isOperationLegalOrCustom(*VPOpcode, WideVT)) {
7371+
EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
7372+
WideVT.getVectorElementCount());
7373+
SDValue Mask = DAG.getAllOnesConstant(dl, WideMaskVT);
7374+
SDValue EVL = DAG.getElementCount(dl, TLI.getVPExplicitVectorLengthTy(),
7375+
OrigVT.getVectorElementCount());
7376+
return DAG.getNode(*VPOpcode, dl, VT, {AccOp, Op, Mask, EVL}, Flags);
7377+
}
7378+
73677379
if (WideVT.isScalableVector()) {
73687380
unsigned GCD = std::gcd(OrigElts, WideElts);
73697381
EVT SplatVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
@@ -7372,14 +7384,14 @@ SDValue DAGTypeLegalizer::WidenVecOp_VECREDUCE_SEQ(SDNode *N) {
73727384
for (unsigned Idx = OrigElts; Idx < WideElts; Idx = Idx + GCD)
73737385
Op = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideVT, Op, SplatNeutral,
73747386
DAG.getVectorIdxConstant(Idx, dl));
7375-
return DAG.getNode(Opc, dl, N->getValueType(0), AccOp, Op, Flags);
7387+
return DAG.getNode(Opc, dl, VT, AccOp, Op, Flags);
73767388
}
73777389

73787390
for (unsigned Idx = OrigElts; Idx < WideElts; Idx++)
73797391
Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem,
73807392
DAG.getVectorIdxConstant(Idx, dl));
73817393

7382-
return DAG.getNode(Opc, dl, N->getValueType(0), AccOp, Op, Flags);
7394+
return DAG.getNode(Opc, dl, VT, AccOp, Op, Flags);
73837395
}
73847396

73857397
SDValue DAGTypeLegalizer::WidenVecOp_VP_REDUCE(SDNode *N) {

‎llvm/lib/IR/StructuralHash.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ namespace {
2424
// by the MergeFunctions pass.
2525

2626
class StructuralHashImpl {
27-
uint64_t Hash;
27+
uint64_t Hash = 4;
2828

2929
void hash(uint64_t V) { Hash = hashing::detail::hash_16_bytes(Hash, V); }
3030

@@ -43,7 +43,7 @@ class StructuralHashImpl {
4343
}
4444

4545
public:
46-
StructuralHashImpl() : Hash(4) {}
46+
StructuralHashImpl() = default;
4747

4848
void updateOperand(Value *Operand) {
4949
hashType(Operand->getType());

‎llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2517,9 +2517,7 @@ static void updateRegisterMapForDbgValueListAfterMove(
25172517
if (RegIt == RegisterMap.end())
25182518
return;
25192519
auto &InstrVec = RegIt->getSecond();
2520-
for (unsigned I = 0; I < InstrVec.size(); I++)
2521-
if (InstrVec[I] == InstrToReplace)
2522-
InstrVec[I] = DbgValueListInstr;
2520+
llvm::replace(InstrVec, InstrToReplace, DbgValueListInstr);
25232521
});
25242522
}
25252523

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp‎

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2002,10 +2002,7 @@ SmallVector<uint32_t, 8> HvxSelector::getPerfectCompletions(ShuffleMask SM,
20022002
if ((unsigned)llvm::popcount(P) < Count) {
20032003
// Reset all occurences of P, if there are more occurrences of P
20042004
// than there are bits in P.
2005-
for (unsigned &Q : Worklist) {
2006-
if (Q == P)
2007-
Q = 0;
2008-
}
2005+
llvm::replace(Worklist, P, 0U);
20092006
}
20102007
}
20112008

‎llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,11 @@ bool NVPTXProxyRegErasure::runOnMachineFunction(MachineFunction &MF) {
7878
assert(InOp.isReg() && "ProxyReg input should be a register.");
7979
assert(OutOp.isReg() && "ProxyReg output should be a register.");
8080
RemoveList.push_back(&MI);
81-
RAUWBatch.try_emplace(OutOp.getReg(), InOp.getReg());
81+
Register replacement = InOp.getReg();
82+
// Check if the replacement itself has been replaced.
83+
if (auto it = RAUWBatch.find(replacement); it != RAUWBatch.end())
84+
replacement = it->second;
85+
RAUWBatch.try_emplace(OutOp.getReg(), replacement);
8286
break;
8387
}
8488
}

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