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fixed bus (#7)
* fixed bus * fmt and clippy
1 parent 85c18f6 commit 4c4adb4

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4 files changed

+152
-126
lines changed

4 files changed

+152
-126
lines changed

Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,6 @@ embedded-hal = "1.0.0"
2020
thiserror = { version = "2.0.3", default-features = false }
2121

2222
[dev-dependencies]
23-
shared-bus = { version= "0.3.1", features=['std'] }
23+
embedded-hal-bus = { version = "0.2.0", features = ["std"] }
2424
embedded-hal-mock = "0.11.1"
2525
rstest = "0.16.0"

src/bus.rs

Lines changed: 119 additions & 110 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
1-
use crate::{address_from_pins, error::MultiplexerError, error::Result as CrateResult};
2-
use embedded_hal::blocking::i2c::{Read, SevenBitAddress, Write, WriteRead};
1+
use crate::address_from_pins;
2+
use crate::prelude::MultiplexerError;
3+
use embedded_hal::i2c::{ErrorType, I2c, Operation, SevenBitAddress};
34

45
pub struct MultiplexerBus {
56
address: u8,
@@ -22,7 +23,7 @@ impl MultiplexerBus {
2223
self
2324
}
2425

25-
pub fn new_port<I2C: 'static + Send + Sync>(&self, i2c: I2C, port: u8) -> BusPort<I2C> {
26+
pub fn new_port<I2C>(&self, i2c: I2C, port: u8) -> BusPort<I2C> {
2627
let id = match port {
2728
0 => 0b000_0001,
2829
1 => 0b000_0010,
@@ -38,83 +39,82 @@ impl MultiplexerBus {
3839
}
3940
}
4041

41-
pub struct BusPort<I2C: 'static + Send + Sync> {
42+
pub struct BusPort<I2C> {
4243
bus: I2C,
4344
address: u8,
4445
port: u8,
4546
}
4647

4748
impl<I2C> BusPort<I2C>
4849
where
49-
I2C: Write + Send + Sync,
50+
I2C: I2c,
5051
{
51-
fn open_port(&mut self) -> CrateResult<()> {
52+
fn open_port(&mut self) -> Result<(), MultiplexerError<I2C::Error>> {
5253
match self.bus.write(self.address, &[self.port]) {
5354
Ok(res) => Ok(res),
54-
Err(_) => Err(MultiplexerError::WriteI2CError),
55+
Err(_) => Err(MultiplexerError::PortError),
5556
}
5657
}
5758
}
5859

59-
impl<I2C> Write for BusPort<I2C>
60+
impl<I2C> ErrorType for BusPort<I2C>
6061
where
61-
I2C: Write + Send + Sync,
62+
I2C: I2c,
6263
{
63-
type Error = MultiplexerError;
64-
65-
fn write(&mut self, address: SevenBitAddress, bytes: &[u8]) -> Result<(), Self::Error> {
66-
self.open_port()?;
67-
match self.bus.write(address, bytes) {
68-
Ok(res) => Ok(res),
69-
Err(_) => Err(MultiplexerError::WriteI2CError),
70-
}
71-
}
64+
type Error = MultiplexerError<I2C::Error>;
7265
}
7366

74-
impl<I2C> Read for BusPort<I2C>
67+
impl<I2C> I2c for BusPort<I2C>
7568
where
76-
I2C: Read + Write + Send + Sync,
69+
I2C: I2c,
7770
{
78-
type Error = MultiplexerError;
79-
80-
fn read(&mut self, address: SevenBitAddress, bytes: &mut [u8]) -> Result<(), Self::Error> {
71+
fn read(&mut self, address: SevenBitAddress, read: &mut [u8]) -> Result<(), Self::Error> {
8172
self.open_port()?;
82-
match self.bus.read(address, bytes) {
83-
Ok(res) => Ok(res),
84-
Err(_) => Err(MultiplexerError::ReadI2CError),
85-
}
73+
self.bus
74+
.read(address, read)
75+
.map_err(|err| MultiplexerError::I2CError(err))
8676
}
87-
}
8877

89-
impl<I2C> WriteRead for BusPort<I2C>
90-
where
91-
I2C: WriteRead + Write + Send + Sync,
92-
{
93-
type Error = MultiplexerError;
78+
fn write(&mut self, address: SevenBitAddress, write: &[u8]) -> Result<(), Self::Error> {
79+
self.open_port()?;
80+
self.bus
81+
.write(address, write)
82+
.map_err(|err| MultiplexerError::I2CError(err))
83+
}
9484

9585
fn write_read(
9686
&mut self,
9787
address: SevenBitAddress,
98-
buffer_in: &[u8],
99-
buffer_out: &mut [u8],
88+
write: &[u8],
89+
read: &mut [u8],
10090
) -> Result<(), Self::Error> {
10191
self.open_port()?;
102-
match self.bus.write_read(address, buffer_in, buffer_out) {
103-
Ok(res) => Ok(res),
104-
Err(_) => Err(MultiplexerError::WriteReadI2CError),
105-
}
92+
self.bus
93+
.write_read(address, write, read)
94+
.map_err(|err| MultiplexerError::I2CError(err))
95+
}
96+
97+
fn transaction(
98+
&mut self,
99+
address: SevenBitAddress,
100+
operations: &mut [Operation<'_>],
101+
) -> Result<(), Self::Error> {
102+
self.open_port()?;
103+
self.bus
104+
.transaction(address, operations)
105+
.map_err(|err| MultiplexerError::I2CError(err))
106106
}
107107
}
108108

109109
#[cfg(test)]
110110
mod test {
111+
extern crate alloc;
111112
use crate::prelude::*;
112-
use embedded_hal::prelude::{
113-
_embedded_hal_blocking_i2c_Read, _embedded_hal_blocking_i2c_Write,
114-
_embedded_hal_blocking_i2c_WriteRead,
115-
};
116-
use embedded_hal_mock::common::Generic;
117-
use embedded_hal_mock::i2c::{Mock, Transaction};
113+
use alloc::vec;
114+
use core::cell::RefCell;
115+
use embedded_hal::i2c::I2c;
116+
use embedded_hal_bus::i2c::RefCellDevice;
117+
use embedded_hal_mock::eh1::i2c::{Mock, Transaction};
118118

119119
#[test]
120120
fn multi_port_write() {
@@ -140,25 +140,28 @@ mod test {
140140
Transaction::write(component_addr, vec![0x45, 0x48]),
141141
];
142142

143-
let i2c = Mock::new(&expectations);
144-
let bus = shared_bus::new_std!(Generic<Transaction> = i2c).unwrap();
143+
let i2c = RefCell::new(Mock::new(&expectations));
145144
let multiplexer = MultiplexerBus::new().with_address(multiplexer_addr);
146145

147-
let mut multiplexed_i2c_a = multiplexer.new_port(bus.acquire_i2c(), ports[0].0);
148-
let mut multiplexed_i2c_b = multiplexer.new_port(bus.acquire_i2c(), ports[1].0);
149-
let mut multiplexed_i2c_c = multiplexer.new_port(bus.acquire_i2c(), ports[2].0);
150-
let mut multiplexed_i2c_d = multiplexer.new_port(bus.acquire_i2c(), ports[3].0);
151-
152-
assert!(multiplexed_i2c_a
153-
.write(component_addr, &[0x05, 0x43])
154-
.is_ok());
155-
assert!(multiplexed_i2c_b.write(component_addr, &[0x55]).is_ok());
156-
assert!(multiplexed_i2c_c
157-
.write(component_addr, &[0x07, 0x39, 0x87])
158-
.is_ok());
159-
assert!(multiplexed_i2c_d
160-
.write(component_addr, &[0x45, 0x48])
161-
.is_ok());
146+
{
147+
let mut multiplexed_i2c_a = multiplexer.new_port(RefCellDevice::new(&i2c), ports[0].0);
148+
let mut multiplexed_i2c_b = multiplexer.new_port(RefCellDevice::new(&i2c), ports[1].0);
149+
let mut multiplexed_i2c_c = multiplexer.new_port(RefCellDevice::new(&i2c), ports[2].0);
150+
let mut multiplexed_i2c_d = multiplexer.new_port(RefCellDevice::new(&i2c), ports[3].0);
151+
152+
assert!(multiplexed_i2c_a
153+
.write(component_addr, &[0x05, 0x43])
154+
.is_ok());
155+
assert!(multiplexed_i2c_b.write(component_addr, &[0x55]).is_ok());
156+
assert!(multiplexed_i2c_c
157+
.write(component_addr, &[0x07, 0x39, 0x87])
158+
.is_ok());
159+
assert!(multiplexed_i2c_d
160+
.write(component_addr, &[0x45, 0x48])
161+
.is_ok());
162+
}
163+
164+
i2c.into_inner().done();
162165
}
163166

164167
#[test]
@@ -185,30 +188,33 @@ mod test {
185188
Transaction::read(component_addr, vec![0x45, 0x48]),
186189
];
187190

188-
let i2c = Mock::new(&expectations);
189-
let bus = shared_bus::new_std!(Generic<Transaction> = i2c).unwrap();
191+
let i2c = RefCell::new(Mock::new(&expectations));
190192
let multiplexer = MultiplexerBus::new().with_address(multiplexer_addr);
191193

192-
let mut multiplexed_i2c_a = multiplexer.new_port(bus.acquire_i2c(), ports[0].0);
193-
let mut multiplexed_i2c_b = multiplexer.new_port(bus.acquire_i2c(), ports[1].0);
194-
let mut multiplexed_i2c_c = multiplexer.new_port(bus.acquire_i2c(), ports[2].0);
195-
let mut multiplexed_i2c_d = multiplexer.new_port(bus.acquire_i2c(), ports[3].0);
194+
{
195+
let mut multiplexed_i2c_a = multiplexer.new_port(RefCellDevice::new(&i2c), ports[0].0);
196+
let mut multiplexed_i2c_b = multiplexer.new_port(RefCellDevice::new(&i2c), ports[1].0);
197+
let mut multiplexed_i2c_c = multiplexer.new_port(RefCellDevice::new(&i2c), ports[2].0);
198+
let mut multiplexed_i2c_d = multiplexer.new_port(RefCellDevice::new(&i2c), ports[3].0);
199+
200+
let mut ma = [0; 2];
201+
assert!(multiplexed_i2c_a.read(component_addr, &mut ma).is_ok());
202+
assert_eq!(ma, [0x05, 0x43]);
196203

197-
let mut ma = [0; 2];
198-
assert!(multiplexed_i2c_a.read(component_addr, &mut ma).is_ok());
199-
assert_eq!(ma, [0x05, 0x43]);
204+
let mut mb = [0; 1];
205+
assert!(multiplexed_i2c_b.read(component_addr, &mut mb).is_ok());
206+
assert_eq!(mb, [0x55]);
200207

201-
let mut mb = [0; 1];
202-
assert!(multiplexed_i2c_b.read(component_addr, &mut mb).is_ok());
203-
assert_eq!(mb, [0x55]);
208+
let mut mc = [0; 3];
209+
assert!(multiplexed_i2c_c.read(component_addr, &mut mc).is_ok());
210+
assert_eq!(mc, [0x07, 0x39, 0x87]);
204211

205-
let mut mc = [0; 3];
206-
assert!(multiplexed_i2c_c.read(component_addr, &mut mc).is_ok());
207-
assert_eq!(mc, [0x07, 0x39, 0x87]);
212+
let mut md = [0; 2];
213+
assert!(multiplexed_i2c_d.read(component_addr, &mut md).is_ok());
214+
assert_eq!(md, [0x45, 0x48]);
215+
}
208216

209-
let mut md = [0; 2];
210-
assert!(multiplexed_i2c_d.read(component_addr, &mut md).is_ok());
211-
assert_eq!(md, [0x45, 0x48]);
217+
i2c.into_inner().done();
212218
}
213219

214220
#[test]
@@ -235,37 +241,40 @@ mod test {
235241
Transaction::write_read(component_addr, vec![0x45, 0x48], vec![0x33, 0x43]),
236242
];
237243

238-
let i2c = Mock::new(&expectations);
239-
let bus = shared_bus::new_std!(Generic<Transaction> = i2c).unwrap();
244+
let i2c = RefCell::new(Mock::new(&expectations));
240245
let multiplexer = MultiplexerBus::new().with_address(multiplexer_addr);
241246

242-
let mut multiplexed_i2c_a = multiplexer.new_port(bus.acquire_i2c(), ports[0].0);
243-
let mut multiplexed_i2c_b = multiplexer.new_port(bus.acquire_i2c(), ports[1].0);
244-
let mut multiplexed_i2c_c = multiplexer.new_port(bus.acquire_i2c(), ports[2].0);
245-
let mut multiplexed_i2c_d = multiplexer.new_port(bus.acquire_i2c(), ports[3].0);
246-
247-
let mut ma = [0x33, 0x43];
248-
assert!(multiplexed_i2c_a
249-
.write_read(component_addr, &[0x05, 0x43], &mut ma)
250-
.is_ok());
251-
assert_eq!(ma, [0x33, 0x43]);
252-
253-
let mut mb = [0x33, 0x43];
254-
assert!(multiplexed_i2c_b
255-
.write_read(component_addr, &[0x55], &mut mb)
256-
.is_ok());
257-
assert_eq!(mb, [0x33, 0x43]);
258-
259-
let mut mc = [0x33, 0x43];
260-
assert!(multiplexed_i2c_c
261-
.write_read(component_addr, &[0x07, 0x39, 0x87], &mut mc)
262-
.is_ok());
263-
assert_eq!(mc, [0x33, 0x43]);
264-
265-
let mut md = [0x33, 0x43];
266-
assert!(multiplexed_i2c_d
267-
.write_read(component_addr, &[0x45, 0x48], &mut md)
268-
.is_ok());
269-
assert_eq!(md, [0x33, 0x43]);
247+
{
248+
let mut multiplexed_i2c_a = multiplexer.new_port(RefCellDevice::new(&i2c), ports[0].0);
249+
let mut multiplexed_i2c_b = multiplexer.new_port(RefCellDevice::new(&i2c), ports[1].0);
250+
let mut multiplexed_i2c_c = multiplexer.new_port(RefCellDevice::new(&i2c), ports[2].0);
251+
let mut multiplexed_i2c_d = multiplexer.new_port(RefCellDevice::new(&i2c), ports[3].0);
252+
253+
let mut ma = [0x33, 0x43];
254+
assert!(multiplexed_i2c_a
255+
.write_read(component_addr, &[0x05, 0x43], &mut ma)
256+
.is_ok());
257+
assert_eq!(ma, [0x33, 0x43]);
258+
259+
let mut mb = [0x33, 0x43];
260+
assert!(multiplexed_i2c_b
261+
.write_read(component_addr, &[0x55], &mut mb)
262+
.is_ok());
263+
assert_eq!(mb, [0x33, 0x43]);
264+
265+
let mut mc = [0x33, 0x43];
266+
assert!(multiplexed_i2c_c
267+
.write_read(component_addr, &[0x07, 0x39, 0x87], &mut mc)
268+
.is_ok());
269+
assert_eq!(mc, [0x33, 0x43]);
270+
271+
let mut md = [0x33, 0x43];
272+
assert!(multiplexed_i2c_d
273+
.write_read(component_addr, &[0x45, 0x48], &mut md)
274+
.is_ok());
275+
assert_eq!(md, [0x33, 0x43]);
276+
}
277+
278+
i2c.into_inner().done();
270279
}
271280
}

src/error.rs

Lines changed: 20 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,13 @@
1+
use embedded_hal::i2c::{Error, ErrorKind};
12
use thiserror::Error;
23

3-
pub type Result<T> = core::result::Result<T, MultiplexerError>;
4+
pub type Result<T, I2cError> = core::result::Result<T, MultiplexerError<I2cError>>;
45

56
#[derive(Error, Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq)]
6-
pub enum MultiplexerError {
7+
pub enum MultiplexerError<I2cError>
8+
where
9+
I2cError: Error,
10+
{
711
#[error("Write Read I2C Error")]
812
WriteReadI2CError,
913
#[error("Write I2C Error")]
@@ -12,4 +16,18 @@ pub enum MultiplexerError {
1216
ReadI2CError,
1317
#[error("Incorrect port supplied")]
1418
PortError,
19+
#[error("I2C Error")]
20+
I2CError(I2cError),
21+
}
22+
23+
impl<I2cError> Error for MultiplexerError<I2cError>
24+
where
25+
I2cError: Error,
26+
{
27+
fn kind(&self) -> ErrorKind {
28+
match self {
29+
Self::I2CError(e) => e.kind(),
30+
_ => ErrorKind::Other,
31+
}
32+
}
1533
}

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