|
42 | 42 | * Define Tx Power
|
43 | 43 | */
|
44 | 44 | #ifndef CFG_TX_POWER
|
45 |
| - #define CFG_TX_POWER (0x18) /* -0.15dBm */ |
| 45 | + #define CFG_TX_POWER (0x18) /* -0.15dBm */ |
46 | 46 | #endif
|
47 | 47 |
|
48 | 48 | /******************************************************************************
|
|
80 | 80 | * This parameter is ignored by the CPU2 when CFG_BLE_OPTIONS has SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY flag set
|
81 | 81 | */
|
82 | 82 | #ifndef CFG_BLE_MAX_ATT_MTU
|
83 |
| - #define CFG_BLE_MAX_ATT_MTU (156) |
| 83 | + #define CFG_BLE_MAX_ATT_MTU (156) |
84 | 84 | #endif
|
85 | 85 |
|
86 | 86 | /**
|
|
104 | 104 | */
|
105 | 105 | // #define CFG_BLE_PREPARE_WRITE_LIST_SIZE BLE_PREP_WRITE_X_ATT(CFG_BLE_MAX_ATT_MTU)
|
106 | 106 | #ifndef CFG_BLE_PREPARE_WRITE_LIST_SIZE
|
107 |
| - #define CFG_BLE_PREPARE_WRITE_LIST_SIZE (0x3A) |
| 107 | + #define CFG_BLE_PREPARE_WRITE_LIST_SIZE (0x3A) |
108 | 108 | #endif
|
109 | 109 |
|
110 | 110 | /**
|
|
118 | 118 | * Enable or disable the Extended Packet length feature. Valid values are 0 or 1.
|
119 | 119 | */
|
120 | 120 | #ifndef CFG_BLE_DATA_LENGTH_EXTENSION
|
121 |
| - #define CFG_BLE_DATA_LENGTH_EXTENSION 1 |
| 121 | + #define CFG_BLE_DATA_LENGTH_EXTENSION 1 |
122 | 122 | #endif
|
123 | 123 |
|
124 | 124 | /**
|
125 | 125 | * Sleep clock accuracy in Slave mode (ppm value)
|
126 | 126 | */
|
127 | 127 | #ifndef CFG_BLE_SLAVE_SCA
|
128 |
| - #define CFG_BLE_SLAVE_SCA 500 |
| 128 | + #define CFG_BLE_SLAVE_SCA 500 |
129 | 129 | #endif
|
130 | 130 |
|
131 | 131 | /**
|
|
140 | 140 | * 7 : 0 ppm to 20 ppm
|
141 | 141 | */
|
142 | 142 | #ifndef CFG_BLE_MASTER_SCA
|
143 |
| - #define CFG_BLE_MASTER_SCA 0 |
| 143 | + #define CFG_BLE_MASTER_SCA 0 |
144 | 144 | #endif
|
145 | 145 |
|
146 | 146 | /**
|
147 | 147 | * LsSource
|
148 | 148 | * Some information for Low speed clock mapped in bits field
|
149 | 149 | * - bit 0: 1: Calibration for the RF system wakeup clock source 0: No calibration for the RF system wakeup clock source
|
150 |
| - * - bit 1: 1: STM32W5M Module device 0: Other devices as STM32WBxx SOC, STM32WB1M module |
| 150 | + * - bit 1: 1: STM32WB5M Module device 0: Other devices as STM32WBxx SOC, STM32WB1M module |
| 151 | + * - bit 2: 1: HSE/1024 Clock config 0: LSE Clock config |
151 | 152 | */
|
152 |
| -#ifndef CFG_BLE_LSE_SOURCE |
| 153 | +#ifndef CFG_BLE_LS_SOURCE |
153 | 154 | #if defined(STM32WB5Mxx)
|
154 |
| - #define CFG_BLE_LSE_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LSE_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LSE_MOD5MM_DEV) |
| 155 | + #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) |
155 | 156 | #else
|
156 |
| - #define CFG_BLE_LSE_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LSE_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LSE_OTHER_DEV) |
| 157 | + #define CFG_BLE_LS_SOURCE (SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB | SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV | SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE) |
157 | 158 | #endif
|
158 | 159 | #endif
|
159 | 160 |
|
160 | 161 | /**
|
161 | 162 | * Start up time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us)
|
162 | 163 | */
|
163 | 164 | #ifndef CFG_BLE_HSE_STARTUP_TIME
|
164 |
| - #define CFG_BLE_HSE_STARTUP_TIME 0x148 |
| 165 | + #define CFG_BLE_HSE_STARTUP_TIME 0x148 |
165 | 166 | #endif
|
166 | 167 |
|
167 | 168 | /**
|
168 | 169 | * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
|
169 | 170 | */
|
170 | 171 | #ifndef CFG_BLE_MAX_CONN_EVENT_LENGTH
|
171 |
| - #define CFG_BLE_MAX_CONN_EVENT_LENGTH (0xFFFFFFFF) |
| 172 | + #define CFG_BLE_MAX_CONN_EVENT_LENGTH (0xFFFFFFFF) |
172 | 173 | #endif
|
173 | 174 |
|
174 | 175 | /**
|
|
190 | 191 | * - SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV
|
191 | 192 | * - SHCI_C2_BLE_INIT_OPTIONS_CS_ALGO2
|
192 | 193 | * - SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2
|
| 194 | + * - SHCI_C2_BLE_INIT_OPTIONS_REDUC_GATTDB_NVM |
| 195 | + * - SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM |
| 196 | + * - SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_USED |
| 197 | + * - SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED |
193 | 198 | * - SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1
|
194 | 199 | * - SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3
|
| 200 | + * - SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_WRITABLE |
| 201 | + * - SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY |
| 202 | + * - SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_SUPPORTED |
| 203 | + * - SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED |
195 | 204 | * which are used to set following configuration bits:
|
196 | 205 | * (bit 0): 1: LL only
|
197 | 206 | * 0: LL + host
|
|
203 | 212 | * 0: extended advertizing not supported
|
204 | 213 | * (bit 4): 1: CS Algo #2 supported
|
205 | 214 | * 0: CS Algo #2 not supported
|
| 215 | + * (bit 5): 1: Reduced GATT database in NVM |
| 216 | + * 0: Full GATT database in NVM |
| 217 | + * (bit 6): 1: GATT caching is used |
| 218 | + * 0: GATT caching is not used |
206 | 219 | * (bit 7): 1: LE Power Class 1
|
207 | 220 | * 0: LE Power Class 2-3
|
| 221 | + * (bit 8): 1: appearance Writable |
| 222 | + * 0: appearance Read-Only |
| 223 | + * (bit 9): 1: Enhanced ATT supported |
| 224 | + * 0: Enhanced ATT not supported |
208 | 225 | * other bits: reserved (shall be set to 0)
|
209 | 226 | */
|
210 | 227 | #define CFG_BLE_OPTIONS (SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY)
|
|
257 | 274 |
|
258 | 275 | #define CFG_BLE_RX_PATH_COMPENS (0)
|
259 | 276 |
|
260 |
| -#endif /* APP_CONF_DEFAULT_H */ |
| 277 | + /* BLE core version (16-bit signed integer). |
| 278 | + * - SHCI_C2_BLE_INIT_BLE_CORE_5_2 |
| 279 | + * - SHCI_C2_BLE_INIT_BLE_CORE_5_3 |
| 280 | + * which are used to set: 11(5.2), 12(5.3). |
| 281 | + */ |
| 282 | + |
| 283 | +#define CFG_BLE_CORE_VERSION (SHCI_C2_BLE_INIT_BLE_CORE_5_3) |
261 | 284 |
|
| 285 | +#endif /* APP_CONF_DEFAULT_H */ |
0 commit comments